资 源 简 介
SPI是一个环形总线结构，由ss（cs）、sck、sdi、sdo构成，其时序其实很简单，主要是在sck的控制下，两个双向移位寄存器进行数据交换。
假设下面的8位寄存器装的是待发送的数据10101010，上升沿发送、下降沿接收、高位先发送。
那么第一个上升沿来的时候 数据将会是sdo=1；寄存器=0101010x。下降沿到来的时候，sdi上的电平将所存到寄存器中去，那么这时寄存器=0101010sdi，这样在8个时钟脉冲以后，两个寄存器的内容互相交换一次。这样就完成里一个spi时序。
-SPI bus is a ring structure, by ss (cs), sck, sdi, sdo composition, its timing is actually very simple, mainly under the control of the sck and two bi-directional shift register for data exchange. Assuming the following 8-bit register is loaded to send the data to be 10,101,010, rising to send, receive falling edge, high first sent. Well, the first rising edge to the time data will be sdo = 1 register = 0101010x. Falling edge comes, sdi on the level will be stored to the register, then register at this time = 0101010sdi, so 8 clock pulse later, the contents of two registers to exchange time. This will be completed in a spi timing.
