资 源 简 介
使用0.18um 标准
CMOS 的工艺设计,内嵌ASIX CORE(32 位RISC 内核,兼容ARM720T,带8KB 指令数
据Cache 和全功能MMU),采用冯诺依曼结构-Using 0.18um standard CMOS process design, embedded ASIX CORE (32 bit RISC core, compatible with ARM720T, with 8KB Data Cache directives and full-featured MMU), the use of the structure of von Neumann