verilog编写的时钟控制程序,在xilinx芯片上开发。具有案件防抖等考虑,-Verilog clock control procedures to prepare, in the Xilinx chip development. Anti-shake, such as with the case considered
SHOW FULL COLUMNS FROM `jrk_downrecords` [ RunTime:0.001150s ]
SELECT `a`.`aid`,`a`.`title`,`a`.`create_time`,`m`.`username` FROM `jrk_downrecords` `a` INNER JOIN `jrk_member` `m` ON `a`.`uid`=`m`.`id` WHERE `a`.`status` = 1 GROUP BY `a`.`aid` ORDER BY `a`.`create_time` DESC LIMIT 10 [ RunTime:0.071141s ]
SHOW FULL COLUMNS FROM `jrk_tagrecords` [ RunTime:0.001018s ]
SELECT * FROM `jrk_tagrecords` WHERE `status` = 1 ORDER BY `num` DESC LIMIT 20 [ RunTime:0.001228s ]
SHOW FULL COLUMNS FROM `jrk_member` [ RunTime:0.000913s ]
SELECT `id`,`username`,`userhead`,`usertime` FROM `jrk_member` WHERE `status` = 1 ORDER BY `usertime` DESC LIMIT 10 [ RunTime:0.003422s ]
SHOW FULL COLUMNS FROM `jrk_searchrecords` [ RunTime:0.000928s ]
SELECT * FROM `jrk_searchrecords` WHERE `status` = 1 ORDER BY `num` DESC LIMIT 5 [ RunTime:0.004254s ]
SELECT aid,title,count(aid) as c FROM `jrk_downrecords` GROUP BY `aid` ORDER BY `c` DESC LIMIT 10 [ RunTime:0.015645s ]
SHOW FULL COLUMNS FROM `jrk_articles` [ RunTime:0.001203s ]
UPDATE `jrk_articles` SET `hits` = 2 WHERE `id` = 122167 [ RunTime:0.011834s ]