关于verilog的各个基本模块的源代码，如加法器，寄存器，选择器及各个测试文件...
资 源 简 介
关于verilog的各个基本模块的源代码，如加法器，寄存器，选择器及各个测试文件-With regard to the various basic modules Verilog source code, such as adders, registers, selectors and the various test file
文 件 列 表
程序
transcript
add.v
addtest.v
alladd.v
alladdtest.v
ALU.v
ALUtest.v
control.v
controltest.v
datapath.v
decoder.v
decodertest.v
dff.v
dfftest.v
ir.v
irtest.v
memory.v
memorytest.v
mux21_32.v
mux21_32test.v
mux21_5.v
mux21_5test.v
mux41_32.v
mux41_32test.v
mux_32.v
mux_32test.v
pc.v
pctest.v
register.v
registerfile.v
registerfiletest.v
registertest.v
TOP.v
TOP_test.v
zerostore.v
