用于FPGA的变长编码算法的HDL编码,包括VHDL及Verilog代码。可用于JPEG及MPEG压缩算法。-Variable-length encoding for FPGA HDL coding algorithms, including VHDL and Verilog code. Can be used in JPEG and MPEG compression algorithms.
SHOW FULL COLUMNS FROM `jrk_downrecords` [ RunTime:0.001057s ]
SELECT `a`.`aid`,`a`.`title`,`a`.`create_time`,`m`.`username` FROM `jrk_downrecords` `a` INNER JOIN `jrk_member` `m` ON `a`.`uid`=`m`.`id` WHERE `a`.`status` = 1 GROUP BY `a`.`aid` ORDER BY `a`.`create_time` DESC LIMIT 10 [ RunTime:0.063275s ]
SHOW FULL COLUMNS FROM `jrk_tagrecords` [ RunTime:0.001049s ]
SELECT * FROM `jrk_tagrecords` WHERE `status` = 1 ORDER BY `num` DESC LIMIT 20 [ RunTime:0.001181s ]
SHOW FULL COLUMNS FROM `jrk_member` [ RunTime:0.000990s ]
SELECT `id`,`username`,`userhead`,`usertime` FROM `jrk_member` WHERE `status` = 1 ORDER BY `usertime` DESC LIMIT 10 [ RunTime:0.003205s ]
SHOW FULL COLUMNS FROM `jrk_searchrecords` [ RunTime:0.000792s ]
SELECT * FROM `jrk_searchrecords` WHERE `status` = 1 ORDER BY `num` DESC LIMIT 5 [ RunTime:0.003928s ]
SELECT aid,title,count(aid) as c FROM `jrk_downrecords` GROUP BY `aid` ORDER BY `c` DESC LIMIT 10 [ RunTime:0.015664s ]
SHOW FULL COLUMNS FROM `jrk_articles` [ RunTime:0.001204s ]
UPDATE `jrk_articles` SET `hits` = 2 WHERE `id` = 123656 [ RunTime:0.019516s ]