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Based on 12 of the MAX502 chip DAC chips in parallel procedures, the use of FPGA...

  • 资源大小:255.09 kB
  • 上传时间:2021-06-30
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  • 资源积分:1积分
  • 标      签: VHDL vhdl

资 源 简 介

基于芯片MAX502的十二位并行DAC芯片的程序,利用FPGA中的ROM查表进行数据存储-Based on 12 of the MAX502 chip DAC chips in parallel procedures, the use of FPGA in the ROM look-up table for data storage

文 件 列 表

db
altsyncram_9b51.tdf
sin12.(0).cnf.cdb
sin12.(0).cnf.hdb
sin12.(1).cnf.cdb
sin12.(1).cnf.hdb
sin12.(2).cnf.cdb
sin12.(2).cnf.hdb
sin12.(3).cnf.cdb
sin12.(3).cnf.hdb
sin12.(4).cnf.cdb
sin12.(4).cnf.hdb
sin12.(5).cnf.cdb
sin12.(5).cnf.hdb
sin12.analyze_file.qmsg
sin12.asm.qmsg
sin12.cbx.xml
sin12.cmp.cdb
sin12.cmp.hdb
sin12.cmp.kpt
sin12.cmp.logdb
sin12.cmp.rdb
sin12.cmp.tdb
sin12.cmp0.ddb
sin12.dbp
sin12.db_info
sin12.eco.cdb
sin12.fit.qmsg
sin12.hier_info
sin12.hif
sin12.map.cdb
sin12.map.hdb
sin12.map.logdb
sin12.map.qmsg
sin12.pre_map.cdb
sin12.pre_map.hdb
sin12.psp
sin12.rtlv.hdb
sin12.rtlv_sg.cdb
sin12.rtlv_sg_swap.cdb
sin12.sgdiff.cdb
sin12.sgdiff.hdb
sin12.signalprobe.cdb
sin12.sld_design_entry.sci
sin12.sld_design_entry_dsc.sci
sin12.syn_hier_info
sin12.tan.qmsg
sin12.bdf
sin12.cdf
sin12.done
sin12.dpf
sin12.fit.rpt
sin12.fit.smsg
sin12.fit.summary
sin12.flow.rpt
sin12.map.rpt
sin12.map.summary
sin12.mif
sin12.pin
sin12.pof
sin12.qpf
sin12.qsf
sin12.qws
sin12.sof
sin12.tan.rpt
sin12.tan.summary
sinn.bsf
sinn.vhd
data_rom.bsf
data_rom.cmp
data_rom.vhd
frediv.vhd
freqdiv.bsf
romgen.c
romgen.exe
sin12.asm.rpt

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