made a ModelSim simulation based on the Verilog source code
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- 上传时间：2021-06-30
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标 签：
嵌入式系统
others
资 源 简 介
发一个基于ModelSim仿真的Verilog源代码包-made a ModelSim simulation based on the Verilog source code
文 件 列 表
keyscan
work
keyscan_test
keyscan
keyscanprj.mpf
vsim.wlf
keyscan.v
keyscan_test.v
modelsim.tcl
keyscanprj.cr.mti
work
convlen3_test
ser2par
covlen
convlen_test.v
dff.v
convl_en.v
covlen3
work
convl3_en
dff.v
convl3_en.v
convlen3_test.v
ASIC_Book_Encoder.mpf
vsim.wlf
ASIC_Book_Encoder.cr.mti
covlen2
work
conv_encode
ConvEncdTestBnch.v
ConEncdJprj.mpf
ConvEncdJA.bak
ConvEncdJA.v
vsim.wlf
ConEncdJprj.cr.mti
HDL_exmple
EX1_MUX
EX2_CNT
EX3_ADD
EX4_VHDL
TRAFFIC.VHD
EX4_VHDL
