用FPGA实现数字锁相环，开发环境为ISE

用FPGA实现数字锁相环，开发环境为ISE-Using FPGA digital phase-locked loop, development environment for ISE

PLL
isim
work
glbl
_xmsgs
__projnav
automake.log
isim.cmd
isim.hdlsourcefiles
isim.log
isimwavedata.xwv
KCounter.isim_lau_exe
KCounter.isim_lau_prj
KCounter.isim_stx_prj
KCounter.isim_stx_sim
Kcounter.sch
KCounter.spl
KCounter.sym
KCounter.v
KCounter_isim_lau.exe
KCounter_lau.prj
KCounter_stx.prj
KCounter_summary.html
Kcounter_test.ant
Kcounter_test.isim_beh_exe
Kcounter_test.isim_beh_log
Kcounter_test.isim_beh_prj
Kcounter_test.jhd
Kcounter_test.tbw
Kcounter_test.tfw
KCounter_test.v
Kcounter_test.xwv
Kcounter_test.xwv_bak
Kcounter_test_beh.prj
Kcounter_test_bencher.prj
Kcounter_test_isim_beh.exe
KCounter_test_v.isim_beh_exe
KCounter_Test_v.isim_beh_log
KCounter_test_v.isim_beh_prj
KCounter_test_v.isim_stx
KCounter_test_v.isim_stx_prj
KCounter_test_v_beh.prj
KCounter_Test_v_isim_beh.exe
KCounter_test_v_stx.prj
PLL.cmd_log
PLL.dhp
PLL.ise
PLL.ise_ISE_Backup
PLL.sch
PLL.schlog
PLL.vf
PLL_summary.html
xilinxsim.ini
__projnav.log
isim.tmp_save
isim.tmp_save
_1
isim
work
glbl
mingw