Quartus II design with three
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- 上传时间：2021-06-30
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标 签：
嵌入式芯片
vhdl
资 源 简 介
用Quartus II 设计的3级流水CPU，指令采用二次重叠执行方式-Quartus II design with three-stage pipeline CPU, instruction execution overlaps with the second time
文 件 列 表
pipeline
db
add_inc.bsf
add_inc.vhd
add_jmp.bsf
add_jmp.vhd
alu.vhd
am.bsf
am.vhd
bus_dir.vhd
bus_mux.bsf
bus_mux.vhd
cmp_state.ini
cpu0.asm.rpt
cpu0.bdf
cpu0.done
cpu0.fit.eqn
cpu0.fit.rpt
cpu0.fit.summary
cpu0.flow.rpt
cpu0.map.eqn
cpu0.map.rpt
cpu0.map.summary
cpu0.pin
cpu0.pof
cpu0.qpf
cpu0.qsf
cpu0.qws
cpu0.sim.rpt
cpu0.sim.vwf
cpu0.sof
cpu0.tan.rpt
cpu0.tan.summary
cpu0.vwf
ctrl_reg.bsf
ctrl_reg.vhd
data_reg.bsf
data_reg.vhd
decoder.bsf
decoder.vhd
Doc1.doc
flag.bsf
flag.vhd
ir.bsf
ir.vhd
pc.bsf
pc.vhd
pc_mux.bsf
pc_mux.vhd
reg.vhd
reg_mux.vhd
reg_out.vhd
reg_test.vhd
reg_testa.bsf
reg_testa.vhd
rom.bsf
rom.vhd
t1.vhd
t2.vhd
t3.vhd
