四进制计数器模块，使用VHDL语言编写，在ISE8.1中经过测试的模型...

四进制计数器模块，使用VHDL语言编写，在ISE8.1中经过测试的模型-quaternary counter module, the use of VHDL language, in which ISE8.1 tested model

FourBitsCounter
xst
work
transcript
templates
isim
_ngo
_xmsgs
FourBitsCounter.ise
coun_summary.html
testwave_bencher.prj
pepExtractor.prj
testwave.xwv
testwave.xwv_bak
testwave.vhw
testwave.ant
testwave.tbw
testwave.jhd
testwave.ado
coun.prj
FourBitsCounter.ise_ISE_Backup
coun.lso
coun.xst
coun.cmd_log
coun.syr
coun.ngr
coun.ngc
coun.stx
coun.bld
coun.ngd
coun_map.mrp
coun_map.ngm
coun.pcf
coun_map.ncd
coun.par
coun.ncd
coun.xpi
coun_pad.csv
coun.pad
coun_pad.txt
coun.unroutes
coun.twx
coun.twr
coun.ut
coun.bgn
coun.drc
coun.bit
_impact.log
_impact.cmd
testwave.udo
testwave.fdo
testwave_gen.prj
xilinxsim.ini
testwave_tbxr.exe
isim.cmd
genExpectedResults.cmd
isim.log
isimwavedata.xwv
testwave.ano
isim.tmp_save
_1
isim.tmp_save
FourBitsCounter.vhd
counter.vhd
FourBitsCounter.udo
FourBitsCounter.fdo
FourBitsCounter.vhd.bak
counter.udo
counter.fdo
counter.vhd.bak
vsim.wlf
coun.vhd
COUNT1.vhd