本代码介绍了使用VHDL开发FPGA的一般流程，最终采用了一种基于FPGA的数字频率的实现方法。该设计采用硬件描述语言VHDL，在软件开发平台ISE上完成，可以...

本代码介绍了使用VHDL开发FPGA的一般流程，最终采用了一种基于FPGA的数字频率的实现方法。该设计采用硬件描述语言VHDL，在软件开发平台ISE上完成，可以在较高速时钟频率（100MHz）下正常工作。该设计的频率计能准确的测量频率在1Hz到100MHz之间的信号。使用ModelSim仿真软件对VHDL程序做了仿真，并完成了综合布局布线，最终下载到芯片Spartan-II上取得良好测试效果。-the code on the FPGA using VHDL development of the general process, finally adopted a FPGA-based digital frequency method. The design using VHDL hardware description language, the software development platform ISE completed, the higher speed clock frequency (100MHz) under normal work. The design of the frequency meter can be accurately measured in a frequency of 100MHz between Hz signal. Use ModelSim VHDL simulation software to do the simulation process, and completed a comprehensive layout cabling, downloaded to the final chip Spartan-II made good on the test results.

Freq_counter
work
xst
_ngo
__projnav
transcript
automake.log
bcd2seg_display.cmd_log
bcd2seg_display.lso
bcd2seg_display.ngr
bcd2seg_display.prj
bcd2seg_display.stx
bcd2seg_display.syr
bcd2seg_display.vhdl
bcd2seg_display_bcd2seg_test_vhd_tb.fdo
bcd2seg_display_bcd2seg_test_vhd_tb.udo
bcd2seg_test.vhd
bitgen.ut
control_unite.cmd_log
control_unite.lso
control_unite.ngr
control_unite.prj
control_unite.stx
control_unite.syr
control_unite.vhdl
control_unite_control_unite_test_vhd_tb.fdo
control_unite_control_unite_test_vhd_tb.udo
control_unite_test.vhd
coregen.log
coregen.prj
counter.cmd_log
counter.lso
counter.ngr
counter.prj
counter.stx
counter.syr
counter.vhdl
counter10.cmd_log
counter10.lso
counter10.ngr
counter10.prj
counter10.stx
counter10.syr
counter10.vhdl
counter10_counter10_test_vhd_tb.udo
counter10_test.vhd
counter_counter_test_vhd_tb.fdo
counter_counter_test_vhd_tb.udo
counter_test.vhd
data_lock.cmd_log
data_lock.lso
data_lock.ngr
data_lock.prj
data_lock.stx
data_lock.syr
data_lock.vhdl
data_lock_data_lock_test_vhd_tb.fdo
data_lock_data_lock_test_vhd_tb.udo
data_lock_test.vhd
free_change.cmd_log
free_change.lso
free_change.ngr
free_change.prj
free_change.stx
free_change.syr
free_change.vhdl
free_change_free_change_test_vhd_tb.udo
free_change_test.vhd
freq_change.cmd_log
freq_change.lso
freq_change.ngr
freq_change.prj
freq_change.stx
freq_change.syr
freq_change.vhdl
freq_change_freq_change_test_vhd_tb.udo
freq_change_test.vhd
Freq_counter.dhp
Freq_counter.npl
gate.vhd
gate.vhdl
gate_teat.vhd
gate_test_vhd_tb.fdo
gate_test_vhd_tb.udo
pepExtractor.prj
prjname.lso
top.bgn
top.bit
top.bld
top.cmd_log
top.drc
top.lfp
top.lso
top.mrp
top.nc1
top.ncd
top.ngc
top.ngd
top.ngm
top.ngr
top.pad
top.pad_txt
top.par
top.pcf
top.placed_ncd_tracker
top.prj
top.routed_ncd_tracker
top.stx
top.syr
top.twr
top.twx
top.ucf
top.ucf.untf
top.ut
Top.vhdl
top.xpi
top_map.ncd
top_map.ngm
top_pad.csv
top_pad.txt
top_test.vhd
top_top_test_vhd_tb.fdo
top_top_test_vhd_tb.udo
vish_stacktrace.vstf
vsim.wlf
_desktop.ini
_pace.ucf
__projnav.log