verilog中调用门级电路的实验程序，实现了门级舰模
资 源 简 介
verilog中调用门级电路的实验程序，实现了门级舰模-call Verilog gate-level circuit of the experimental procedures, to achieve a gate-level ship-mode
文 件 列 表
gate
g
simulation
work
db
gate.qpf
gate.qsf
gate.map.rpt
gate.flow.rpt
gate.map.summary
gate.map.eqn
gate.fit.eqn
gate.pin
gate.fit.rpt
gate.fit.summary
gate.sof
gate.pof
gate.asm.rpt
gate.tan.summary
gate.tan.rpt
gate.done
flop.bsf
gate.bdf
gate.vwf
gate.sim.rpt
gate.vt
gate.eda.rpt
quartus_nativelink_simulation.log
vsim.wlf
testben.mpf
Waveform1.vwf
Waveform1.vt
Waveform1.v
testben.cr.mti
gate.qws
flop.v
cmp_state.ini
