这是一个介绍32位RISC处理器软核的设计与验证

这是一个介绍32位RISC处理器软核的设计与验证-Introduction This is a soft 32-bit RISC processor core design and verification

sent_receive
work
isim
xst
__projnav
_xmsgs
transcript
vsim.wlf
fa_tbw.vhw
fa_tbw.ant
sent_receive.ise
fa1_tbw.xwv
fa_tbw_bencher.prj
fa1_tbw_bencher.prj
sent_receive.ise_ISE_Backup
fa1_tbw.xwv_bak
fa1_tbw.vhw
fa1_tbw.ant
fa1_tbw.tbw
sent_receive.dhp
fa_v.vhd
fa_v.ngr
fa_v.ngc
fa_v.stx
fa2_tbw_bencher.prj
fa2_tbw.xwv
fa2_tbw.xwv_bak
fa2_tbw.vhw
fa2_tbw.ant
fa2_tbw.tbw
rcv_v.vhd
fa2_tbw.udo
fa2_tbw.fdo
rcv_v.prj
rcv_v.lso
rcv_v.cmd_log
rcv_v.syr
rcv_v.ngr
rcv_v.ngc
rcv_v.stx
rcv_v_summary.html
rcv_tbw_bencher.prj
rcv_tbw.xwv
rcv_tbw.xwv_bak
rcv_tbw.vhw
rcv_tbw.ant
rcv_tbw.tbw
fa_v.spl
rcv_tbw.udo
rcv_tbw.fdo
fa_v.sym
rcv_v.spl
pepExtractor.prj
fa_tbw.xwv
fa_tbw.xwv_bak
rcv_v.sym
sent_receive_sch.sch
prjname.lso
fa_tbw.tbw
sent_receive_sch.cmd_log
sent_receive_sch.vhf
sent_receive_tbw_bencher.prj
sent_receive_tbw.xwv
sent_receive_tbw.xwv_bak
sent_receive_tbw.vhw
sent_receive_tbw.ant
sent_receive_tbw.tbw
sent_receive_sch.prj
sent_receive_tbw.udo
sent_receive_tbw.fdo
sent_receive_sch.lso
__projnav.log
automake.log
fa_v.prj
isim.cmd
fa_v.cmd_log
sent_receive_sch.stx
results.txt
fa_v.syr
sent_receive_sch_vhdl.prj
fa_v.lso
sent_receive_tbw.jhd
fa_tbw.jhd
fa_v_summary.html
rcv_tbw_beh.prj
rcv_tbw.isim_beh_prj
xilinxsim.ini
rcv_tbw_isim_beh.exe
rcv_tbw.isim_beh_exe
rcv_tbw.isim_beh_log
isimwavedata.xwv
isim.hdlsourcefiles
fa_tbw_isim_beh.exe
fa_tbw.isim_beh_log
sent_receive_tbw_beh.prj
sent_receive_tbw.isim_beh_prj
unisim.auxlib
vcomponents
vcomponents.h
sent_receive_tbw_isim_beh.exe
sent_receive_tbw.isim_beh_exe
sent_receive_tbw.isim_beh_log
sent_receive_sch_summary.html
fa_tbw_gen.prj
fa_tbw.isim_gen_prj
fa_tbw.isim_gen_exe
isim.tmp_save
_1
fa_tbw_tbxr.exe
isim.log
fa_tbw.ano
fa_tbw_beh.prj
fa_tbw.isim_beh_prj
fa_tbw.isim_beh_exe
fa_tbw.udo
fa_tbw.fdo
unisim.auxlib
isim.tmp_save