Verilog实现的VGA程序，用ISE打开工程文件即可

Verilog实现的VGA程序，用ISE打开工程文件即可-Verilog implementation VGA program, open the project file with the ISE can be

vga
__projnav
xst
automake.log
coregen.log
coregen.prj
generic_dpram.v
generic_spram.v
prjname.lso
sync_check.v
tests.v
tests.v.bak
test_bench_top.v
test_bench_top.v.bak
timescale.v
vga.dhp
vga.npl
vga_clkgen.v
vga_colproc.v
vga_csm_pb.v
vga_curproc.v
vga_cur_cregs.v
vga_defines.v
vga_defines.v.bak
vga_enh_top.cmd_log
vga_enh_top.lso
vga_enh_top.prj
vga_enh_top.stx
vga_enh_top.syr
vga_enh_top.v
vga_enh_top_vhdl.prj
vga_fifo.v
vga_fifo_dc.v
vga_pgen.v
vga_tgen.v
vga_vtim.v
vga_wb_master.v
vga_wb_master.v.bak
vga_wb_slave.v
vga_wb_slave.v.bak
wb_b3_check.v
wb_b3_check.v.bak
wb_mast_model.v
wb_model_defines.v
wb_model_defines.v.bak
wb_slv_model.v
wb_slv_model.v.bak
__projnav.log