索FPGA Verilog使用ROM和RAM实现高dcfifo
资 源 简 介
alteral FPGA VERILOG 利用 ROM DCFIFO 和RAM
实现高速到低速时钟域的数据传输 ，值得学习。-alteral FPGA VERILOG using ROM DCFIFO and RAM to realize high-speed low-speed clock domain data transfer, it is worth learning.
文 件 列 表
an_dcfifo_top_restored
simulation
db
an473.pdf
an_dcfifo_top.qarlog
an_dcfifo_top.qpf
an_dcfifo_top.qsf
an_dcfifo_top.qws
an_dcfifo_top.v
an_dcfifo_top_assignment_defaults.qdf
an_dcfifo_top_fast_to_slow.sdc
an_dcfifo_top_fast_to_slow.vwf
an_dcfifo_top_slow_to_fast.sdc
an_dcfifo_top_slow_to_fast.vwf
assignment_defaults.qdf
dcfifo8X32.v
myrom.hex
ram256X32.v
ram256X32_bb.v
read_control_logic.v
rom256X32.v
write_control_logic.v
