本设计是针对LEON3 Altera Nios II startix2

This leon3 design is tailored to the Altera NiosII Startix2 Development board, with 16-bit DDR SDRAM and 2 Mbyte of SSRAM. As of this time, the DDR interface only works up to 120 MHz. At 130, DDR data can be read but not written. NOTE: the test bench cannot be simulated with DDR enabled because the Altera pads do not have the correct delay models. * How to program the flash prom with a FPGA programming file 1. Create a hex file of the programming file with Quartus. 2. Convert it to srecord and adjust the load address: objcopy --adjust-vma=0x800000 output_file.hexout -O srec fpga.srec 3. Program the flash memory using grmon: flash erase 0x800000 0xb00000 flash load fpga.srec-This leon3 design is tailored to the Altera NiosII Startix2 Development board, with 16-bit DDR SDRAM and 2 Mbyte of SSRAM. As of this time, the DDR interface only works up to 120 MHz. At 130, DDR data can be read but not written. NOTE: the

leon3-altera-ep2s60-ddr
linkprom
indata
defconfig
.config
ahbrom.vhd
config.help
config.in
config.vhd
config.vhd.h
config.vhd.in
config_test.h
lconfig.tk
leon3mp.vhd
output_file.cof
prom.h
prom.srec
README.txt
sdram.srec
smc_mctrl.vhd
sram.srec
systest.c
testbench.vhd
tkconfig.h
wave.do
Makefile