VHDL实现SPI功能源代码

VHDL实现SPI功能源代码 -- The SPI bus is a 3 wire bus that in effect links a serial shift -- register between the "master" and the "slave". Typically both the -- master and slave have an 8 bit shift register so the combined -- register is 16 bits. When an SPI transfer takes place, the master and -- slave shift their shift registers 8 bits and thus exchange their 8 -- bit register values.-SPI realize the functional VHDL source code The SPI bus is a 3 wire bus that in effect links a serial shift register between the

spi
LIB.DLS
spi(1).cnf
spi(2).cnf
spi(3).cnf
spi(4).cnf
spi(5).cnf
spi(6).cnf
spi(7).cnf
spi(8).cnf
spi(9).cnf
spi.acf
spi.cnf
spi.hif
spi.mmf
spi.ndb
SPI.sym
spi.vhd
U0200221.DLS
U1754406.DLS
U2561360.DLS
U2918138.DLS
U3670051.DLS
U4824688.DLS
U8712012.DLS