用VHDL编写的FIR数字滤波器的程序可以用在FPGA工作。

FIR数字滤波器程序，采用vhdl编写，可用于FPGA电路-FIR digital filter procedure for the preparation of VHDL can be used in FPGA circuit

16AdderBalanced.vhd
16ADDERBALANCED_old.vhd
1BITADDER.VHD
1bitpfa.vhd
4bitcla.vhd
8bitreg3.vhd
ADDERDELAY.VHD
BalancedMult.VHD
CoefficientTest.vhd
comb0.vhd
comb1.vhd
comb2.vhd
comb3.vhd
counter.vhd
DelayBlock.VHD
EnableALL3.vhd
FinalBalancedFIR.vhd
FinalBalancedFIR2.vhd
hc.vhd
mcell11.vhd
mcell21.vhd
mcell210.vhd
mcell212.vhd
mcell214.vhd
MCELL21_1.VHD
mcell22.vhd
mcell24.vhd
mcell26.vhd
mcell28.vhd
mcell31.vhd
mcell41.vhd
mcell51.vhd
mcell61.vhd
mcell71.vhd
MCELLnone.VHD
newslice.vhd
orblock.vhd
orcomp.vhd
orpart2.vhd
sinetest.vhd
SineTest4KSample1.1Ksignal.vhd
SineTest4KSample1Ksignal.vhd
SineTest4KSample500Hzsignal.vhd
sinetesttenK.vhd
tapadder.vhd
TAPCONTROL.VHD
tb_balancedtest.vhd
ttldtype.vhd
ttlNodelays.vhd
xorblock.vhd