The code has a lot on learning verilog HDL examples have help for beginners
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资 源 简 介
该代码中有不少关于学习verilog HDL的例子,对初学者有帮助-The code has a lot on learning verilog HDL examples have help for beginners
文 件 列 表
source files
string.v
half_adder.v
audio_dac.v
arith_test.v
read_mem.v.bak
task_example.v
task_example.v.bak
logical_test.v
relat_test.v
equal_test.v
bit_test.v
reduct_test.v
shift_test.v
mux_2_1.v.bak
my_dff.v
my_dff.v.bak
mux_2_1.v
fff2.v
connect_test.v
fff1.v
fff2.v.bak
testmemory.v
testmemory.v.bak
ex1.v
mytest.v
mytest.v.bak
ex2.v
ex2.v.bak
ex3.v
ex3.v.bak
ex4.v
ex4.v.bak
unknown.v
unknown.v.bak
about_time.v
traffic_lights.v
random_function.v
random_function.v.bak
mux4_1.v
mux4_1.v.bak
my_carry.v
my_carry.v.bak
my_sum.v
adder_test.v
traffic_lights.v.bak
register_initialize.v
register_initialize.v.bak
demo_multiout_function.v
shift_register_3.v
shift_register_3.v.bak
clk_counter.v
demo_multiout_function.v.bak
clk_counter_test.v
clk_counter.v.bak
clk_counter_test.v.bak
8shift_register.v
8shift_register.v.bak
level_and_edge_sensitive_compare.v
level_and_edge_sensitive_compare.v.bak
timing_control_inner_mode.v.bak
timing_control_inner_mode.v
full_adder_1.v
full_adder_1.v.bak
dff.bak
dff_asychronous.v
ex1.v.bak
clk_gen.v
clk_gen.v.bak
clk_gen1.v
clk_gen1.v.bak
counter.v
counter.v.bak
counter1.v
counter1.v.bak
8bits_multiplier.v
8bits_multiplier.v.bak
_8bits_multiplier1.v
_8bits_multiplier1.v.bak
left_shifter_4.v
left_shifter_4.v.bak
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