The document may download to FPGA chip to complete the clock divider,serial
- 资源大小：1.11 MB
- 上传时间：2021-06-30
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- 资源积分：1积分
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标 签：
VHDL
vhdl
资 源 简 介
本文件是可以直接使用下载到FPGA里面使用，里面包含时钟分频电路，串并转换和并串转换电路，多通道信号加权的乘加电路等。-The document may download to FPGA chip to complete the clock divider,serial-to-parallel,parallel-to-serial,and multiple-add circuit for multiple channels weight calculation
文 件 列 表
signal_output
db
.sopc_builder
install.ptf
altmult_add1.bsf
altmult_add1.cmp
altmult_add1.vhd
altmult_add1_wave0.jpg
altmult_add1_waveforms.html
altpll1.bsf
altpll1.cmp
altpll1.ppf
altpll1.vhd
altpll1_wave0.jpg
altpll1_waveforms.html
clk_counter.bsf
clk_counter.vhd
clk_even_divdier.bsf
clk_even_divdier.vhd
fdecode.bsf
fdecode.vhd
ingerate.bsf
ingerate.vhd
lpm_add1.bsf
lpm_add1.cmp
lpm_add1.vhd
LPM_ADD_SUB1.bsf
LPM_ADD_SUB1.cmp
LPM_ADD_SUB1.vhd
lpm_add_sub2.bsf
lpm_add_sub2.cmp
lpm_add_sub2.vhd
lpm_constant1.bsf
lpm_constant1.cmp
lpm_constant1.vhd
lpm_fa.vhd
lpm_ff1.bsf
lpm_ff1.cmp
lpm_ff1.vhd
LPM_INV1.bsf
LPM_INV1.cmp
LPM_INV1.vhd
lpm_inv2.bsf
lpm_inv2.cmp
lpm_inv2.vhd
lpm_latch1.bsf
lpm_latch1.cmp
lpm_latch1.vhd
lpm_xor1.bsf
lpm_xor1.cmp
lpm_xor1.vhd
prune.bsf
prune.vhd
ps_transform.bsf
ps_transform.v
ps_transform2.bsf
ps_transform2.vhd
signal_output.asm.rpt
signal_output.bdf
signal_output.done
signal_output.dpf
signal_output.fit.rpt
signal_output.fit.summary
signal_output.flow.rpt
signal_output.jdi
signal_output.map.rpt
signal_output.map.smsg
signal_output.map.summary
signal_output.merge.rpt
signal_output.pin
signal_output.pof
signal_output.qpf
signal_output.qsf
signal_output.qws
signal_output.sim.rpt
signal_output.sof
signal_output.tan.rpt
signal_output.tan.summary
signal_output.vwf
signal_output_assignment_defaults.qdf
sopc_builder_debug_log.txt
sp_transform.bsf
sp_transform.vhd
sp_transform1.bsf
sp_transform1.v
sp_transform_cos.bsf
sp_transform_cos.vhd
sp_transform_sin.bsf
sp_transform_sin.vhd
Waveform1.vwf
Waveform2.vwf
weight_cos.bsf
weight_cos.vhd
weight_sin.bsf
weight_sin.vhd
.sopc_builder
