资 源 简 介
直接数字频率合成器（Direct Digital Frequency Synthesizer：DDFS）的VHDL程序,开发环境是QuartusII,系统时钟为50MHz，由PLL产生DDFS的工作时钟166.67MHz,地址位宽为24位，频率字为20，相位字为10，RAM用于存储查找表，其地址位宽为10，数据位宽为8。-Direct Digital Frequency Synthesizer ( DDFS) of the VHDL program, the development environment is QuartusII, the system clock to 50MHz, the work of DDFS generated by PLL clock 166.67MHz, address bit-width of 24-bit frequency word is 20, phase word for 10, RAM used to store look-up table, its address is 10 bits wide, the data is 8 bits wide.
文 件 列 表
ddfsdemo
greybox_tmp
db
transcript
DDFSCore.bsf
DDFSCore.vhd
ddfsdemo.asm.rpt
ddfsdemo.bdf
ddfsdemo.done
ddfsdemo.dpf
ddfsdemo.fit.rpt
ddfsdemo.fit.smsg
ddfsdemo.fit.summary
ddfsdemo.flow.rpt
ddfsdemo.map.rpt
ddfsdemo.map.summary
ddfsdemo.pin
ddfsdemo.pof
ddfsdemo.qpf
ddfsdemo.qsf
ddfsdemo.qws
ddfsdemo.sim.rpt
ddfsdemo.sof
ddfsdemo.tan.rpt
ddfsdemo.tan.summary
DualPortRam.bsf
DualPortRam.cmp
DualPortRam.vhd
DualPortRam_wave0.jpg
DualPortRam_wave1.jpg
DualPortRam_waveforms.html
MCUInterFace.bsf
MCUInterface.vhd
pll.bsf
pll.cmp
pll.ppf
pll.vhd
pll_waveforms.html
prev_cmp_ddfsdemo.qmsg
sin_ram2_1024.mif
undo_redo.txt
vish_stacktrace.vstf
