基于FPGA的中值滤波

使用Verilog HDL语言实现的中值滤波木块，可以应用到相关图像处理中或者数据处理中。

image_process
simulation
incremental_db
greybox_tmp
db
Gray_Median_Filter.v
Gray_Median_Filter.v.bak
image_process.asm.rpt
image_process.done
image_process.eda.rpt
image_process.fit.rpt
image_process.fit.smsg
image_process.fit.summary
image_process.flow.rpt
image_process.map.rpt
image_process.map.summary
image_process.pin
image_process.qpf
image_process.qsf
image_process.sof
image_process.sta.rpt
image_process.sta.summary
image_process.v
image_process.v.bak
image_process_nativelink_simulation.rpt
Line_Shift_RAM_8Bit.bsf
Line_Shift_RAM_8Bit.cmp
Line_Shift_RAM_8Bit.inc
Line_Shift_RAM_8Bit.qip
Line_Shift_RAM_8Bit.v
Line_Shift_RAM_8Bit_bb.v
Line_Shift_RAM_8Bit_inst.v
Matrix_Generate_3X3_8Bit.v
Matrix_Generate_3X3_8Bit.v.bak
Median_Filter_3X3.v
Sort3.v