VHDL在FPGA计数器

应用背景本程序给出了如何为 计数器应用信息；BASYS2 board，这是一个从Digilent为那些不熟悉它的FPGA板。关键技术它展示了如何建立一个计数器和建立在ISE格式项目所需步骤，应用写作的计数器的VHDL代码，写引脚约束文件（。UCF）最后为BASYS2 board位文件。

CounterApp.gise
CounterApp.xise
CounterApp_ise12migration.zip
fuse.log
fuse.xmsgs
fuseRelaunch.cmd
isim.cmd
isim.log
main.bgn
main.bit
main.bld
main.cmd_log
main.drc
main.lso
main.ncd
main.ngc
main.ngd
main.ngr
main.pad
main.par
main.pcf
main.prj
main.ptwx
main.stx
main.syr
main.twr
main.twx
main.unroutes
main.ut
main.vhd
main.xpi
main.xst
main_beh.prj
main_bitgen.xwbt
main_envsettings.html
main_guide.ncd
main_isim_beh.exe
main_isim_beh.wdb
main_map.map
main_map.mrp
main_map.ncd
main_map.ngm
main_map.xrpt
main_ngdbuild.xrpt
main_pad.csv
main_pad.txt
main_par.xrpt
main_summary.html
main_summary.xml
main_usage.xml
main_vhdl.prj
main_xst.xrpt
pins.ucf
usage_statistics_webtalk.html
webtalk.log
webtalk_pn.xml
xilinxsim.ini
_ngo
netlist.lst
_xmsgs
bitgen.xmsgs
map.xmsgs
ngdbuild.xmsgs
par.xmsgs
pn_parser.xmsgs
trce.xmsgs
xst.xmsgs
ipcore_dir
iseconfig
CounterApp.projectmgr
main.xreport
isim
isim_usage_statistics.html
main_isim_beh.exe.sim
pn_info
precompiled.exe.sim
work
xlnx_auto_0_xdb
cst.xbcd
xst
dump.xst
projnav.tmp
work
counter_logic.png
counter_logic2.png