FPGA实现全加器

用Verilog HDL实现一个全加器,全加器英语名称为full-adder，是用门电路实现两个二进制数相加并求出和的组合线路，称为一位全加器。一位全加器可以处理低位进位，并输出本位加法进位。多个一位全加器进行级联可以得到多位全加器。常用二进制四位全加器74LS283。

simulation
modelsim
incremental_db
compiled_partitions
README
db
add_all.(0).cnf.cdb
add_all.(0).cnf.hdb
add_all.amm.cdb
add_all.asm.qmsg
add_all.asm.rdb
add_all.cbx.xml
add_all.cmp.kpt
add_all.cmp.rdb
add_all.cmp0.ddb
add_all.cmp1.ddb
add_all.cmp2.ddb
add_all.cmp_merge.kpt
add_all.db_info
add_all.eda.qmsg
add_all.fit.qmsg
add_all.hier_info
add_all.hif
add_all.idb.cdb
add_all.lpc.html
add_all.lpc.rdb
add_all.lpc.txt
add_all.map.bpm
add_all.map.cdb
add_all.map.hdb
add_all.map.kpt
add_all.map.logdb
add_all.map.qmsg
add_all.map_bb.cdb
add_all.map_bb.hdb
add_all.map_bb.logdb
add_all.pre_map.cdb
add_all.pre_map.hdb
add_all.rtlv.hdb
add_all.rtlv_sg.cdb
add_all.rtlv_sg_swap.cdb
add_all.sgdiff.cdb
add_all.sgdiff.hdb
add_all.sld_design_entry.sci
add_all.sld_design_entry_dsc.sci
add_all.smart_action.txt
add_all.sta.qmsg
add_all.sta.rdb
add_all.syn_hier_info
add_all.tis_db_list.ddb
logic_util_heursitic.dat
prev_cmp_add_all.qmsg
add_all.asm.rpt
add_all.done
add_all.eda.rpt
add_all.fit.rpt
add_all.fit.summary
add_all.flow.rpt
add_all.map.rpt
add_all.map.summary
add_all.pin
add_all.pof
add_all.qpf
add_all.qsf
add_all.sof
add_all.sta.rpt
add_all.sta.summary
add_all.v
add_all.v.bak
add_all_nativelink_simulation.rpt
add_all_tb.v
add_all_tb.v.bak
Vhdl1.vhd
Vhdl1.vhd.bak