UART模块

在FPGA上用Verilog实现的UART串口通信模块，包含分频模块，接收模块，发送模块，可以更改波特率，适合初学者学习，已经在板子上得到了验证。

uart_16
_xmsgs
_ngo
xst
xlnx_auto_0_xdb
iseconfig
ipcore_dir
CK.v
ck_ucf.ucf
clkdiv.cmd_log
clkdiv.lso
clkdiv.ngc
clkdiv.ngr
clkdiv.prj
clkdiv.rar
clkdiv.stx
clkdiv.syr
clkdiv.v
clkdiv.xst
clkdiv_envsettings.html
clkdiv_summary.html
clkdiv_xst.xrpt
uartrx.v
uarttx.v
uart_16.bgn
uart_16.bit
uart_16.bld
uart_16.cmd_log
uart_16.drc
uart_16.gise
uart_16.lso
uart_16.ncd
uart_16.ngc
uart_16.ngd
uart_16.ngr
uart_16.pad
uart_16.par
uart_16.pcf
uart_16.prj
uart_16.ptwx
uart_16.stx
uart_16.syr
uart_16.twr
uart_16.twx
uart_16.unroutes
uart_16.ut
uart_16.v
uart_16.xise
uart_16.xpi
uart_16.xst
uart_16_bitgen.xwbt
uart_16_envsettings.html
uart_16_guide.ncd
uart_16_map.map
uart_16_map.mrp
uart_16_map.ncd
uart_16_map.ngm
uart_16_map.xrpt
uart_16_ngdbuild.xrpt
uart_16_pad.csv
uart_16_pad.txt
uart_16_par.xrpt
uart_16_summary.html
uart_16_summary.xml
uart_16_usage.xml
uart_16_xst.xrpt
usage_statistics_webtalk.html
webtalk.log
webtalk_pn.xml