锁相环Verilog代码

锁相环是通信领域最基本的元件，同时在FPGA上也有广泛的应用，本代码是锁相环PLL的Verilog HDL代码，简单易读，能够实现PLL基本的锁相、分频等功能

PLL
automake.log
iseconfig
isim.cmd
isim.hdlsourcefiles
isim.log
isim.tmp_save
isimwavedata.xwv
KCounter.isim_lau_prj
KCounter.isim_stx_prj
KCounter.isim_stx_sim
Kcounter.sch
KCounter.spl
KCounter.sym
KCounter.v
KCounter_isim_lau.exe
KCounter_lau.prj
KCounter_stx.prj
KCounter_summary.html
Kcounter_test.ant
Kcounter_test.isim_beh_log
Kcounter_test.jhd
Kcounter_test.tbw
Kcounter_test.tfw
KCounter_test.v
Kcounter_test.xwv
Kcounter_test.xwv_bak
Kcounter_test_bencher.prj
Kcounter_test_isim_beh.exe
KCounter_Test_v.isim_beh_log
KCounter_test_v.isim_stx
KCounter_test_v.isim_stx_prj
KCounter_test_v_beh.prj
KCounter_Test_v_isim_beh.exe
KCounter_test_v_stx.prj
PLL.cmd_log
PLL.dhp
PLL.gise
PLL.ise_ISE_Backup
PLL.jhd
PLL.lso
PLL.prj
PLL.sch
PLL.syr
PLL.vf
PLL.xise
PLL.xst
PLL_envsettings.html
PLL_summary.html
PLL_xdb
PLL_xst.xrpt
sch2HdlBatchFile
webtalk_pn.xml
work
xilinxsim.ini
xst
_xmsgs
__projnav.log