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FPGA I2C IP

  • 资源大小:583.44 kB
  • 上传时间:2021-06-30
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  • 标      签: Verilog verilog

资 源 简 介

应用背景i2cSlave is a minimalist I2C slave IP core that provides the basic framework for the implementation of custom I2C slave devices. The core provides a means to read and write up to 256 8-byte registers. These registers can be connected to the users custom logic, thus implementing a simple control and status interface.关键技术The core has up 256 registers that can be accessed via I2C. I2C write operations are used to set the register address pointer, and write the register data. I2C reads are used to read the register data. Successive data reads or writes result in data being read or written from incremental register addresses. There is no limit on how much data can be read or written in a single access, but the internal register address pointer will wrap round to 0 once it reaches 255. Note that the address pointer is not initialized at reset, and the address pointer must

文 件 列 表

I2C_Slave
i2cSlave.v
i2cSlaveTop.v
i2cSlave_define.v
i2cSlave_FSM.pdf
i2cSlave_IPCore_Specification.pdf
registerInterface.v
serialInterface.v
timescale.v

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