用VHDL写的源代码程序，包涵三人表决器，七人表决器，全加器以及模24，模60的计数器，都是单文件的，由于程序小又多，所以集中在一起，供新学习VHDL语言的朋友们参考。-With VHDL source code written procedures, includes three of the voting machine, vote on seven people, and full adder, as well as modulus 24, modulus 60 counters, are single-file, as many small procedures, so together for the new Learning VHDL Language Reference friends.
SHOW FULL COLUMNS FROM `jrk_downrecords` [ RunTime:0.001398s ]
SELECT `a`.`aid`,`a`.`title`,`a`.`create_time`,`m`.`username` FROM `jrk_downrecords` `a` INNER JOIN `jrk_member` `m` ON `a`.`uid`=`m`.`id` WHERE `a`.`status` = 1 GROUP BY `a`.`aid` ORDER BY `a`.`create_time` DESC LIMIT 10 [ RunTime:0.084858s ]
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SHOW FULL COLUMNS FROM `jrk_member` [ RunTime:0.000985s ]
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SHOW FULL COLUMNS FROM `jrk_articles` [ RunTime:0.001162s ]
UPDATE `jrk_articles` SET `hits` = 2 WHERE `id` = 225949 [ RunTime:0.014040s ]
