组合电路与时序电路的 VHDL 代码

下面给定 zip 包含各项的组合电路与时序电路设计的 vhdl 代码二进制加法器 （全以及一半）、 二进制比较器、 二进制交易加法器，bcd 码与二进制并行加法器，j k 翻转翻牌，像拿倒了计数器，计数器等十年对抗等以及源代码、 测试台架波形 (ubuntu 支持) 还提供了 pdf 和屏幕截图的 RTL 原理图和技术示意图。

assign1-1
gates-tbw.pdf
main code.docx
screenshots
test bench code.docx
assign1-10
jk flipflop-tbw.pdf
main code.docx
screenshots
test bench code.docx
assign1-11a
main code.docx
screenshots
test bench code.docx
udcounter.pdf
assign1-11b
decadecounter-tbw.pdf
main code.docx
screenshots
test bench code.docx
assign1-2
main code.docx
onebitcomparator.pdf
screenshots
test bench code.docx
assign1-3
fourbitcomparator-tbw.pdf
main code.docx
screenshots
test bench code.docx
assign1-4
full adder behav.pdf
main code.docx
screenshots
test bench code.docx
assign1-5
component half adder code.docx
component OR code.docx
fulladder_hadder_tbw.pdf
main full adder code.docx
screenshots
test bench code.docx
assign1-6
bpa-tbw.pdf
component full adder code.docx
main bpa code.docx
screenshots
test bench code.docx
assign1-7a
bcd-with-bpa.pdf
component bpa code.docx
component full adder code.docx
main code.docx
screenshots
test bench code.docx
assign1-7b
bcd-without-bpa-tbw.pdf
main code.docx
screenshots
test bench code.docx
assign1-8
main code.docx
screenshots
t_ff_tbw.pdf
test bench code.docx
assign1-9
d_ff_tbw.pdf
main code.docx
screenshots
test bench code.docx