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A complete viterbi coding procedures, the use of VHDL language, as well as test...

  • 资源大小:222.68 kB
  • 上传时间:2021-06-30
  • 下载次数:0次
  • 浏览次数:1次
  • 资源积分:1积分
  • 标      签: VHDL vhdl

资 源 简 介

一个完整的viterbi编码程序,使用vhdl语言编写,还有测试程序-A complete viterbi coding procedures, the use of VHDL language, as well as test procedures

文 件 列 表

testbench
auk_vit_vit_var_enc_arc_rtl.vhd
auk_vit_vit_var_enc_ent.vhd
Bench_vit_par_atl_arc_ben_node_sync.vhd
Bench_vit_par_atl_ent_node_sync.vhd
viterbi_node_sync_testbench.vhd
vi_bench.vhd
vi_functions.vhd
vi_interface.vhd
source
a_rcvsym.txt
a_txsym.txt
ber_node_sync.vhd
BER_report.txt
ber_threshold.vhd
block_period_stim.txt
mux_2d.vhd
rotate_node_sync.vhd
tcm_rcv_sector.txt
transbit.txt
viterbi_BER.bsf
viterbi_BER.cmp
viterbi_BER.html
viterbi_BER.inc
viterbi_BER.vhd
viterbi_BER.vho
viterbi_BER_bb.v
viterbi_BER_inst.vhd
viterbi_BER_logiclock_script.tcl
viterbi_BER_testbench.vhd
viterbi_BER_vital_script.tcl
viterbi_BER_vsim_script.tcl
viterbi_node_sync.vhd
Quartus_II
run_script.tcl
viterbi_node_sync.qpf
viterbi_node_sync.qsf
wave.do

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