数字时钟Verilog

数字时钟的Verilog程序，用quartus打开就能使用，可以用做课程设计、电子设计等使用

程序
2014111272.asm.rpt
2014111272.bdf
2014111272.done
2014111272.dpf
2014111272.fit.rpt
2014111272.fit.smsg
2014111272.fit.summary
2014111272.flow.rpt
2014111272.map.rpt
2014111272.map.smsg
2014111272.map.summary
2014111272.pin
2014111272.pof
2014111272.qpf
2014111272.qsf
2014111272.qws
2014111272.sim.rpt
2014111272.sof
2014111272.tan.rpt
2014111272.tan.summary
2014111272.vwf
21selector.v.bak
alarm.bsf
alarm.v
alarm.v.bak
counter10.bsf
counter10.v
counter10.v.bak
counter24.bsf
counter24.v
counter24.v.bak
counter6.bsf
counter6.v
counter6.v.bak
db
divider1000.bsf
divider500.bsf
divider500.v
divider500.v.bak
division.vwf
dvd1000.bsf
dvd1000.v
dvd2.bsf
dvd2.v
incremental_db
selector.bsf
selector.v
shumaguan.bsf
shumaguan.v
sound.bsf
sound.v
top_clock.bsf
top_clock.v
top_clock.v.bak
Waveform1.vwf
Waveform12.vwf
zdbs.bsf
zdbs.v