计数器BCD

Este projeto é referente a um relógio digital com 6 displays 7-segmentos, representado no formato HH:MM:SS. A versão inicial do projeto trata-se de construir um bloco com 3 contadores BCD representado em displays 7-segmentos, contando de 000 a 999. O mesmo será utilizado como componente no projeto do relógio.

Contador_Decada_BCD
incremental_db
db
Count_Dec_BCD.asm.rpt
Count_Dec_BCD.done
Count_Dec_BCD.fit.rpt
Count_Dec_BCD.fit.summary
Count_Dec_BCD.flow.rpt
Count_Dec_BCD.map.rpt
Count_Dec_BCD.map.summary
Count_Dec_BCD.pin
Count_Dec_BCD.pof
Count_Dec_BCD.qpf
Count_Dec_BCD.qsf
Count_Dec_BCD.qws
Count_Dec_BCD.sim.rpt
Count_Dec_BCD.sof
Count_Dec_BCD.tan.rpt
Count_Dec_BCD.tan.summary
Count_Dec_BCD.vhd
Count_Dec_BCD.vhd.bak
Count_Dec_BCD.vwf
PCT_COUNT_DEC_BCD.vhd
PCT_COUNT_DEC_BCD.vhd.bak
BCD_7_Seg
incremental_db
db
BCD_7SEG.asm.rpt
BCD_7SEG.done
BCD_7SEG.fit.rpt
BCD_7SEG.fit.summary
BCD_7SEG.flow.rpt
BCD_7SEG.map.rpt
BCD_7SEG.map.summary
BCD_7SEG.pin
BCD_7SEG.pof
BCD_7SEG.qpf
BCD_7SEG.qsf
BCD_7SEG.qws
BCD_7SEG.sim.rpt
BCD_7SEG.sof
BCD_7SEG.tan.rpt
BCD_7SEG.tan.summary
BCD_7SEG.vhd
BCD_7SEG.vhd.bak
BCD_7SEG.vwf
AND_2
incremental_db
db
AND_2.asm.rpt
AND_2.done
AND_2.fit.rpt
AND_2.fit.summary
AND_2.flow.rpt
AND_2.map.rpt
AND_2.map.summary
AND_2.pin
AND_2.pof
AND_2.qpf
AND_2.qsf
AND_2.qws
AND_2.sim.rpt
AND_2.sof
AND_2.tan.rpt
AND_2.tan.summary
AND_2.vhd
AND_2.vhd.bak
AND_2.vwf
NAND_2
incremental_db
db
NAND_2.asm.rpt
NAND_2.done
NAND_2.fit.rpt
NAND_2.fit.summary
NAND_2.flow.rpt
NAND_2.map.rpt
NAND_2.map.summary
NAND_2.pin
NAND_2.pof
NAND_2.qpf
NAND_2.qsf
NAND_2.qws
NAND_2.sim.rpt
NAND_2.sof
NAND_2.tan.rpt
NAND_2.tan.summary
NAND_2.vhd
NAND_2.vwf
FF_T
incremental_db
db
FF_T.asm.rpt
FF_T.done
FF_T.fit.rpt
FF_T.fit.summary
FF_T.flow.rpt
FF_T.map.rpt
FF_T.map.summary
FF_T.pin
FF_T.pof
FF_T.qpf
FF_T.qsf
FF_T.qws
FF_T.sim.rpt
FF_T.sof
FF_T.tan.rpt
FF_T.tan.summary
FF_T.vhd
FF_T.vhd.bak
FF_T.vwf