100例VHDL语言解释，北京理工大学毕业…

VHDL语言100例详解，北京理工大学ASIC研究生出版，这里是51~94个examples-VHDL language of 100 cases explain, Beijing Institute of Technology, Graduate ASIC publication, here is the 51 ~ 94 examples

51_test_113
51_test_113.vhd
94_SPARC
README.TXT
93_WSS
90_wss_component.vhd
90_wss_subtype.vhd
93_WSS.VHD
93_wss_top.vhd
README.TXT
92_WSS
90_wss_component.vhd
90_wss_subtype.vhd
92_wss_stringreg.vhd
README.TXT
91_WSS
90_wss_component.vhd
90_wss_subtype.vhd
91_wss_mem_sequence.vhd
README.TXT
90_WSS
90_wss_component.vhd
90_wss_coprocessor.vhd
90_wss_subtype.vhd
README.TXT
89_full_adder
89_Full_adder.vhd
89_full_adder_stim.vhd
89_pack_2_0.vhd
README.TXT
88_arms_counter
88_ARMS_COUNTER.vhd
88_arms_counter_stim.vhd
88_pack_2_0.vhd
README.TXT
87_control
87_control.vhd
87_control_stim.vhd
README.TXT
86_STACK
86_STACK.VHD
86_stack_stim.vhd
README.TXT
85_UPC
85_UPC.VHD
85_upc_stim.vhd
README.TXT
84_REG
84_REG.VHD
84_reg_stim.vhd
README.TXT
83_multiplexer
83_multiplexer.vhd
83_multiplexer_stim.vhd
README.TXT
82_output_shifter
82_output_and_shifter.vhd
82_output_shifter_stim.vhd
README.TXT
81_Q_REG
81_Q_REG.VHD
81_q_reg_stim.vhd
README.TXT
80_MEM
80_MEM.VHD
80_mem_stim.vhd
README.TXT
79_ALU
79_ALU.VHD
79_test_vectors.vhd
README.TXT
78_alu_input
78_alu_inputs.vhd
78_test_vectors.vhd
README.TXT
77_NPS
README.TXT
76_PID
76_Fpu.vhd
76_Pid.vhd
76_pid_stim.vhd
README.TXT
75_RAM
35_bit_pack.vhd
75_RAM.VHD
README.TXT
74_alarm_clock
69_p_alarm_clock.vhd
74_alarm_clock.vhd
74_tb_alarm_clock.vhd
README.TXT
73_alarm_fq
69_p_alarm_clock.vhd
73_fq_divider.vhd
73_tb_fq_divider.vhd
README.TXT
72_alarm_display
69_p_alarm_clock.vhd
72_display_driver.vhd
72_tb_display_driver.vhd
README.TXT
71_alarm_counter
69_p_alarm_clock.vhd
71_alarm_counter.vhd
71_alarm_reg.vhd
71_tb_alarm_counter.vhd
71_tb_alarm_reg.vhd
README.TXT
70_alarm_buffer
69_p_alarm_clock.vhd
70_buffer.vhd
70_tb_buffer.vhd
README.TXT
69_decoder
69_decoder.vhd
69_p_alarm_clock.vhd
69_tb_decoder.vhd
README.TXT
68_alarm_controller
68_alarm_controller.vhd
68_tb_alarm_controller.vhd
69_p_alarm_clock.vhd
README.TXT
67_ellipf
67_ellipf.vhd
67_PACK.VHD
67_test_vector.vhd
README.TXT
66_FIR
66_FIR.VHD
66_PACK.VHD
66_signed.vhd
66_testfir.vhd
README.TXT
65_conditioner
65_conditioner.VHD
65_conditioner_stim.VHD
README.TXT
64_TLC
64_test_vectors.vhd
64_TLC.VHD
README.TXT
63_gcd_disp
63_gcd_disp.vhd
63_STIM.VHD
63_VHDL.VHD
README.TXT
62_GCD
62_GCD.VHD
62_gcd_stim.vhd
README.TXT
61_assign
61_assign.vhd
61_Logic.vhd
README.TXT
59_decoder
59_decoder.vhd
58_decoder
58_decoder.vhd
57_instruction_dec
57_instruction_dec.vhd
56_prefetch
56_prefetch.vhd
56_STIM.VHD
56_Vhdl.vhd
README.TXT
55_falsepath
55_falsepath.vhd
55_falsepath_stim.vhd
README.TXT
54_display
54_display.vhd
54_display_stim.vhd
README.TXT
53_counter
53_counter.vhd
53_counter_testbench.vhd
README.TXT
52_divider
52_DIVIDER.vhd
52_Divider_stim.vhd
README.TXT