cpu32 _加法器

介绍 verilog 语言，用于实现包括乘法计算两个 32 位数字。在码，我输入我的 CWID 和 41411 来验证功能。您可以更改要计算不同的值的十六进制文件。体系结构 ︰ 携带-波纹 + 进位跳跃。

bonus
code.hex
cpu32_cmp.v
cpu32_test.v
carry_skip
WORK
.routing_guide.rgf
.tmp.cfp
area.final
cell.rep
code.hex
command.log
compile_dc.tcl
compile_dc.tcl~
cpu32.conn.rpt
cpu32.cts_trace
cpu32.geom.rpt
cpu32.sdc
cpu32.v
cpu32.vh
cpu32_modify.v~
cpu32_test.v
cts.rguide
CTS_RP_MOVE.txt
default.svf
encounter.cmd
encounter.cmd1
encounter.conf
encounter.conf~
encounter.cts
encounter.log
encounter.log1
encounter.tcl
encounter.tcl.old_jan2014
final.dspf
final.gds2
final.v
fm_shell_command.log
formality.log
gds2_encounter.map
gds2_virtuoso.map
gscl45nm.v
ipo1.txt
ipo2.txt
libManager.log
power.final
power.rep
report.ctsmdl
report.ctsrpt
report.post_troute.ctsrpt
shm.db
shm.dsn
skew.post_troute_local.ctsrpt
timing.rep
timing.rep.1.placed
timing.rep.2.ipo1
timing.rep.3.cts
timing.rep.4.ipo2
timing.rep.5.final
verilog.log
.cadence
dfII
viva
.cadence
shm.db
carry_ripple
WORK
FM_WORK3
FM_WORK2
FM_WORK1
FM_WORK
.routing_guide.rgf
.simvision
dbrowser-bookmarks
.tmp.cfp
adder32.v
area.final
cell.rep
code.hex
command.log
compile_dc.tcl
compile_dc.tcl~
cpu32.conn.rpt
cpu32.conn.rpt.old
cpu32.cts_trace
cpu32.geom.rpt
cpu32.geom.rpt.old
cpu32.sdc
cpu32.v
cpu32.vh
cpu32.v~
cpu32_0.v
cpu32_test.v
cts.rguide
CTS_RP_MOVE.txt
default.svf
encounter.cmd
encounter.cmd1
encounter.cmd2
encounter.conf
encounter.conf~
encounter.cts
encounter.log
encounter.log1
encounter.log2
encounter.tcl
encounter.tcl.old_jan2014
final.dspf
final.gds2
final.v
fm_shell_command.lck
fm_shell_command.log
fm_shell_command1.lck
fm_shell_command1.log
fm_shell_command2.lck
fm_shell_command2.log
fm_shell_command3.lck
fm_shell_command3.log
fm_shell_command4.log
formality.lck
formality.log
formality1.lck
formality1.log
formality2.lck
formality2.log
formality3.lck
formality3.log
formality4.log
gds2_encounter.map
gds2_virtuoso.map
gscl45nm.v
ipo1.txt
ipo2.txt
power.final
power.rep
report.ctsmdl
report.ctsrpt
report.post_troute.ctsrpt
shm.db
shm.dsn
skew.post_troute_local.ctsrpt
timing.rep
timing.rep.1.placed
timing.rep.2.ipo1
timing.rep.3.cts
timing.rep.4.ipo2
timing.rep.5.final
verilog.log
.cadence
edi
workspaces
.cadence
.simvision
shm.db
ECE429 Final project.pdf