Verilog written procedures for counting frequency meter module,
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标 签:
VHDL
vhdl
资 源 简 介
verilog写的频率计程序的计数模块,-Verilog written procedures for counting frequency meter module,
文 件 列 表
counter
db
counter.qpf
counter.qsf
counter.qws
cmp_state.ini
counter.map.rpt
counter.flow.rpt
counter.map.summary
counter.map.eqn
counter.fit.eqn
counter.pin
counter.fit.rpt
counter.fit.summary
counter.pof
counter.asm.rpt
counter.tan.summary
counter.tan.rpt
counter.done
counter.vwf
counter.sim.rpt
counter10.v
Waveform1.vwf
counter.v
counter.bsf