异步数据包的数据路径组件实例

Actually doing practical asynchronous design can be hard to learn, simply because of the lack of examples. This project has some example code that you can look at, and maybe use. First is a random number generator. It uses a linear feedback shift register to generate a lot of 16-bit pseudo-random numbers quickly. Mathematically it"s not so good, but for some things it"s good enough -- and it"s certainly fast and cheap. Second is code for a CRC-16 checksum, using the CCITT standard polynomial. Both of these components use four-phase handshaking. They"re written in gate-level Verilog which should be synthesizable. The testbench code has been tested in Icarus Verilog but should run in similar tools like Modelsim.

bdcrc16
Makefile
tests
crc16.c
crc16.v