在FPGA高速ADC-ADC08D1000沟通

这是由阿龙利开发的程序，以控制ADC08D1000模拟 - 数字设备中的FPGA，赛灵思的Virtex-4 SX35 FPGA此处应用，DCM的用于控制FPGA中的时钟路径，所述时钟源是AD9517该PLC控制的FPGA中的串行端口

AD2Gg(3.28)
AUTO_FIFO_WR.vhd
AUTO_FIFO_WR.vhi
d500.ucf
DATA_JOIN.vhd
dcm1.vhd
dcm1.xaw
dcm1_arwz.ucf
dcm_dclk.vhd
dcm_dclk.xaw
dcm_dclk_arwz.ucf
top.ngr
demo.ise_ISE_Backup
demo.ntrc_log
top.ngc
demo.ise
demo_ise9migration.zip
fifo4k.asy
fifo4k.edn
fifo4k.ngo
fifo4k.sym
fifo4k.v
fifo4k.veo
fifo4k.vhd
fifo4k.vho
fifo4k.xco
fifo4k_fifo_generator_v3_2_xst_1.lso
fifo4k_fifo_generator_v3_2_xst_1.ngc
fifo4k_fifo_generator_v3_2_xst_1_vhdl.prj
fifo4k_flist.txt
fifo4k_readme.txt
fifo4k_xmdf.tcl
FIFO_DIN.cpj
FIFO_DOUT.cpj
fifo_generator_release_notes.txt
fifo_generator_ug175.pdf
FIFO_OUT_OK(328).mcs
FIFO_OUT_OK(328).prm
FIFO_OUT_OK(328).sig
FIFO_OUT_OK.bit
LVDSTRANS.vhd
MODLE_DATA_CH.vhd
param.opt
pepExtractor.prj
PLL_CONTROL.vhd
templates
coregen.xml
top.bgn
top.bit
top.bld
top.cmd_log
top.drc
top.lso
top.ncd
top_cs.blc
top.ngd
top_cs.ngc
top.pad
top.par
top.pcf
top.prj
top_vhdl.prj
top.syr
top.twr
top.twx
top.unroutes
top.ut
top.vhd
top.xpi
top.xst
TOP2.vhd
top_chip.cdc
demo.restore
top_guide.ncd
top_map.map
top_map.mrp
top_map.ngm
top_map.ncd
top_pad.csv
top_pad.txt
top_prev_built.ngd
top_summary.html
top_summary.xml
top_usage.xml
_impact.cmd
TO_MAIN_BOARD.mcs
TO_MAIN_BOARD.prm
TO_MAIN_BOARD.sig
two_dcm.vhd
top.stx
_impact.log
Untitled.prm
Untitled.sig
xaw2vhdl.log
xst
dump.xst
top.prj
ntrc.scr
ws330.mcs
ws328.mcs
_ngo
icon_pro.ncf
_xmsgs
xst.xmsgs
ln331.mcs
ln331.prm
ln331.sig
ws330.prm
ws330.sig
ws331.mcs
ws331.prm
ws331.sig
fifo_clk_dcm.xaw
fifo_clk_dcm_arwz.ucf
fifo_clk_dcm.vhd
fifo_clk_dcm.vhi
ws331(2).mcs
ws331(2).prm
ws331(2).sig
ws331(3).mcs
ws331(3).prm
ws331(3).sig
top_chip2.cdc
tmp
_cg
templates
tmp
xst
_ngo
_xmsgs
AD9517_SERIAL_CONTROL.vhd
AD2Gg(3.28)