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您现在的位置是:虫虫源码 > 其他 > FPGA驱动DM9000

FPGA驱动DM9000

  • 资源大小:7.10 MB
  • 上传时间:2021-06-30
  • 下载次数:0次
  • 浏览次数:1次
  • 资源积分:1积分
  • 标      签: Verilog

资 源 简 介

通过FPGA驱动DM9000的程序源代码,可以实现UDP协议传输,长时间测试速率不掉,可以参考

文 件 列 表

CD0_UDP_NET
UDPtester
system_0_sim
Sdram_Control_4Port
incremental_db
IMAG_READ
hello_world_1_syslib
hello_world_1
greybox_tmp
DM9000A
CD0_NET_syslib
tmp
system_0_generation_script
.metadata
.bak_0.log
.sopc_builder
filters.xml
altera.components
.cdtproject
CD0_NET.asm.rpt
CD0_NET.cdf
CD0_NET.done
CD0_NET.dpf
CD0_NET.fit.rpt
CD0_NET.fit.smsg
CD0_NET.fit.summary
CD0_NET.flow.rpt
CD0_NET.jdi
CD0_NET.map.rpt
CD0_NET.map.smsg
CD0_NET.map.summary
CD0_NET.pin
CD0_NET.pof
CD0_NET.qpf
CD0_NET.qsf
CD0_NET.qsf.bak
CD0_NET.sof
CD0_NET.sta.rpt
CD0_NET.sta.summary
CD0_NET.v
CD0_NET.v.bak
CONTROL.v
cpu_0.ocp
cpu_0.sdc
cpu_0.v
cpu_0_bht_ram.mif
cpu_0_dc_tag_ram.mif
cpu_0_ic_tag_ram.mif
cpu_0_jtag_debug_module_sysclk.v
cpu_0_jtag_debug_module_tck.v
cpu_0_jtag_debug_module_wrapper.v
cpu_0_mult_cell.v
cpu_0_ociram_default_contents.mif
cpu_0_oci_test_bench.v
cpu_0_rf_ram_a.mif
cpu_0_rf_ram_b.mif
cpu_0_test_bench.v
DM9000A.v
dm9000a_0.v
DM9000A_IF.v
dma_0.v
DN9000A.v
epcs_flash_controller_0.v
epcs_flash_controller_0_boot_rom.hex
I2C_Controller.v
I2C_OV5620_Config.v
IMRD.v
jtag_uart_0.v
KEY.v
LEDR.v
onchip_memory2_0.hex
onchip_memory2_0.v
OV5620_Capture.v
PIO.v
PLL1.ppf
PLL1.qip
PLL1.v
Reset_Delay.v
sdram_0.v
sdram_0_test_component.v
SDRAM_PLL.bsf
SDRAM_PLL.ppf
SDRAM_PLL.qip
SDRAM_PLL.v
sopc_add_qip_file.tcl
sopc_builder_log.txt
SPI_CONFIG.v
SPI_MASTER.v
system_0.bsf
system_0.html
system_0.ptf
system_0.ptf.8.0
system_0.ptf.bak
system_0.ptf.pre_generation_ptf
system_0.qip
system_0.sopc
system_0.sopcinfo
system_0.v
system_0_burst_0.v
system_0_burst_1.v
system_0_clock_0.v
system_0_clock_1.v
system_0_inst.v
system_0_log.txt
web_check_log.txt
.metadata
.sopc_builder
altera.components

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