四位全加器的Verilog源代码

应用背景小的verilog程序，实现一四位全加器的功能。它有两大模块。一个是四位全加器，另一个是一位全加器，它是采用组合逻辑，不复杂，但简洁明了。这将是一个很好的第一步，学习verillog。适合初学者练习。关键技术只是Verilog和组合逻辑实现一四位加法器。它建立了2个模块。一个是大 ；框架，其他作品如子功能。家庭 ；spratan-3e XC3S100E，设备，包装cp132。全加器意味着它有一个进位，它可以显示的进行，如果过流发生。

adder2
_xmsgs
_ngo
xst
xlnx_auto_0_xdb
isim
iseconfig
ipcore_dir
add.v
adder2.bgn
adder2.bit
adder2.bld
adder2.cmd_log
adder2.drc
adder2.gise
adder2.lso
adder2.ncd
adder2.ngc
adder2.ngd
adder2.ngr
adder2.pad
adder2.par
adder2.pcf
adder2.prj
adder2.ptwx
adder2.stx
adder2.syr
adder2.twr
adder2.twx
adder2.unroutes
adder2.ut
adder2.v
adder2.xise
adder2.xpi
adder2.xst
adder2_bitgen.xwbt
adder2_envsettings.html
adder2_guide.ncd
adder2_isim_beh1.wdb
adder2_map.map
adder2_map.mrp
adder2_map.ncd
adder2_map.ngm
adder2_map.xrpt
adder2_ngdbuild.xrpt
adder2_pad.csv
adder2_pad.txt
adder2_par.xrpt
adder2_summary.html
adder2_summary.xml
adder2_tb.v
adder2_tb_beh.prj
adder2_tb_isim_beh.exe
adder2_tb_isim_beh.wdb
adder2_usage.xml
adder2_xst.xrpt
add_isim_beh.exe
contraints.ucf
fuse.log
fuse.xmsgs
fuseRelaunch.cmd
isim.cmd
isim.log
usage_statistics_webtalk.html
webtalk.log
webtalk_pn.xml
xilinxsim.ini