资 源 简 介
基于FPGA(Field-Programmable Gate Array)的OFDM(Orthogonal Frequency Division Multiplexing)信号传输系统VHDL源码
use IEEE.std_logic_unsigned.all;
package outconverter is
constant stage : natural := 3;
constant FFTDELAY:integer:=13+2*STAGE;
constant FACTORDELAY:integer:=6;
constant OUTDELAY:integer:=9;
function counter2addr(
counter : std_logic_vector;
mask1:std_logic_vector;
mask2:std_logic_vector
) return std_logic_vector;
function outcounter2addr(counter : std_logic_vector) return std_logic_vector;
end outconverter;
package body outconverter is
function counter2addr(
counter : std_logic_vector;
mask1:std_logic_vector;
mask2:std_logic_vector
) return std_logic_vector is
variable result :std_logic_vector(counter"range);
begin
for n in mask1"range loop
if mask1(n)="1" then
result( 2*n+1 downto 2*n ):=counter( 1 downto 0 );
elsif mask2(n)="1" and n/=STAGE-1
文 件 列 表
_xmsgs
transcript
cfft4.vhd
cfft.vhd
cfft_control.vhd
conj.vhd
counter.vhd
div4limit.vhd
FPGA Implementation of an OFDM Modem.ppt
input.vhd
interface.vhd
inv_control.vhd
io_control.vhd
juntos.vhd
modem.vhd
modem_summary.html
mulfactor.vhd
mux.vhd
mux_control.vhd
OFDM - portuguese.pdf
ofdm.ise
ofdm.ise_ISE_Backup
ofdm.npl
ofdm.npl_ISE_Backup
ofdm.vhd
ofdm_ise7_bak.zip
outconvert.vhd
output.vhd
p2r_cordic.vhd
p2r_CordicPipe.vhd
parallel.vhd
qam.vhd
qamdecoder.vhd
ram.vhd
ram_control.vhd
rofactor.vhd
rxmodem.vhd
sc_corproc.vhd
serial.vhd
serparser.vhd
starts.vhd
startup_timer.vhd
tx_control.vhd
txmodem.vhd
txrx.vhd
blockdram.vhd
