文 件 列 表
CED1.asm.rpt
CED1.done
CED1.dpf
CED1.eda.rpt
CED1.fit.rpt
CED1.fit.summary
CED1.flow.rpt
CED1.hexout
CED1.map.rpt
CED1.map.summary
CED1.pin
CED1.pof
CED1.qpf
CED1.qsf
CED1.sof
CED1.tan.rpt
CED1.tan.summary
ReadMe.txt
serv_req_info.txt
sim.bat
.svn
all-wcprops
entries
format
prop-base
CED1.pof.svn-base
text-base
CED1.asm.rpt.svn-base
all-wcprops
entries
format
all-wcprops
entries
format
all-wcprops
entries
format
all-wcprops
entries
format
all-wcprops
entries
format
all-wcprops
entries
format
all-wcprops
entries
format
all-wcprops
entries
format
all-wcprops
entries
format
all-wcprops
entries
format
all-wcprops
entries
format
all-wcprops
entries
format
all-wcprops
entries
format
all-wcprops
entries
format
all-wcprops
entries
format
all-wcprops
entries
format
all-wcprops
entries
format
all-wcprops
entries
format
all-wcprops
entries
format
all-wcprops
entries
format
all-wcprops
entries
format
all-wcprops
entries
format
all-wcprops
entries
format
all-wcprops
entries
format
all-wcprops
entries
format
all-wcprops
entries
format
.svn\props\
.svn\tmp\prop-base\
.svn\tmp\props\
.svn\tmp\text-base\
db
altsyncram_esm1.tdf
CED1.(0).cnf.cdb
CED1.(0).cnf.hdb
CED1.(1).cnf.cdb
CED1.(1).cnf.hdb
CED1.(10).cnf.cdb
CED1.(10).cnf.hdb
CED1.(11).cnf.cdb
CED1.(11).cnf.hdb
CED1.(12).cnf.cdb
CED1.(12).cnf.hdb
CED1.(13).cnf.cdb
CED1.(13).cnf.hdb
CED1.(14).cnf.cdb
CED1.(14).cnf.hdb
CED1.(15).cnf.cdb
CED1.(15).cnf.hdb
CED1.(16).cnf.cdb
CED1.(16).cnf.hdb
CED1.(17).cnf.cdb
CED1.(17).cnf.hdb
CED1.(18).cnf.cdb
CED1.(18).cnf.hdb
CED1.(19).cnf.cdb
CED1.(19).cnf.hdb
CED1.(2).cnf.cdb
CED1.(2).cnf.hdb
CED1.(20).cnf.cdb
CED1.(20).cnf.hdb
CED1.(21).cnf.cdb
CED1.(21).cnf.hdb
CED1.(22).cnf.cdb
CED1.(22).cnf.hdb
CED1.(23).cnf.cdb
CED1.(23).cnf.hdb
CED1.(24).cnf.cdb
CED1.(24).cnf.hdb
CED1.(25).cnf.cdb
CED1.(25).cnf.hdb
CED1.(3).cnf.cdb
CED1.(3).cnf.hdb
CED1.(4).cnf.cdb
CED1.(4).cnf.hdb
CED1.(5).cnf.cdb
CED1.(5).cnf.hdb
CED1.(6).cnf.cdb
CED1.(6).cnf.hdb
CED1.(7).cnf.cdb
CED1.(7).cnf.hdb
CED1.(8).cnf.cdb
CED1.(8).cnf.hdb
CED1.(9).cnf.cdb
CED1.(9).cnf.hdb
CED1.asm.qmsg
CED1.cbx.xml
CED1.cmp.bpm
CED1.cmp.cdb
CED1.cmp.ecobp
CED1.cmp.hdb
CED1.cmp.logdb
CED1.cmp.rdb
CED1.cmp.tdb
CED1.cmp0.ddb
CED1.cmp_bb.cdb
CED1.cmp_bb.hdb
CED1.cmp_bb.logdb
CED1.cmp_bb.rcf
CED1.dbp
CED1.db_info
CED1.eco.cdb
CED1.eda.qmsg
CED1.fit.qmsg
CED1.hier_info
CED1.hif
CED1.map.bpm
CED1.map.cdb
CED1.map.ecobp
CED1.map.hdb
CED1.map.logdb
CED1.map.qmsg
CED1.map_bb.cdb
CED1.map_bb.hdb
CED1.map_bb.logdb
CED1.merge_hb.atm
CED1.pre_map.cdb
CED1.pre_map.hdb
CED1.psp
CED1.pss
CED1.rtlv.hdb
CED1.rtlv_sg.cdb
CED1.rtlv_sg_swap.cdb
CED1.sgdiff.cdb
CED1.sgdiff.hdb
CED1.sld_design_entry.sci
CED1.sld_design_entry_dsc.sci
CED1.smp_dump.txt
CED1.syn_hier_info
CED1.tan.qmsg
CED1.tis_db_list.ddb
prev_cmp_CED1.asm.qmsg
prev_cmp_CED1.eda.qmsg
prev_cmp_CED1.fit.qmsg
prev_cmp_CED1.map.qmsg
prev_cmp_CED1.qmsg
prev_cmp_CED1.tan.qmsg
example interface code
AD7760_sample_code.c
AD7760_sample_code.dsp
AD7760_sample_code.dsw
AD7760_sample_code.ncb
AD7760_sample_code.opt
AD7760_sample_code.plg
ADI_CED1_dll.c
ADI_CED1_dll.h
samples.csv
.svn
Debug
AD7760_sample_code.exe
example interface code\.svn\props\
example interface code\.svn\tmp\prop-base\
example interface code\.svn\tmp\props\
example interface code\.svn\tmp\text-base\
example interface code\Debug\.svn\props\
example interface code\Debug\.svn\tmp\prop-base\
example interface code\Debug\.svn\tmp\props\
example interface code\Debug\.svn\tmp\text-base\
simulation
.svn
modelsim
CED1.vo
simulation\.svn\prop-base\
simulation\.svn\props\
simulation\.svn\text-base\
simulation\.svn\tmp\prop-base\
simulation\.svn\tmp\props\
simulation\.svn\tmp\text-base\
simulation\modelsim\.svn\props\
simulation\modelsim\.svn\tmp\prop-base\
simulation\modelsim\.svn\tmp\props\
simulation\modelsim\.svn\tmp\text-base\
simulation\modelsim\rtl_work\parallel\
simulation\modelsim\rtl_work\parallel_new\
simulation\modelsim\rtl_work\parallel_rx\
simulation\modelsim\rtl_work\spi\
simulation\modelsim\rtl_work\.svn\prop-base\
simulation\modelsim\rtl_work\.svn\props\
simulation\modelsim\rtl_work\.svn\tmp\prop-base\
simulation\modelsim\rtl_work\.svn\tmp\props\
simulation\modelsim\rtl_work\.svn\tmp\text-base\
simulation\modelsim\rtl_work\@c@e@d1\.svn\props\
simulation\modelsim\rtl_work\@c@e@d1\.svn\tmp\prop-base\
simulation\modelsim\rtl_work\@c@e@d1\.svn\tmp\props\
simulation\modelsim\rtl_work\@c@e@d1\.svn\tmp\text-base\
simulation\modelsim\rtl_work\@c@e@d1_tb\.svn\props\
simulation\modelsim\rtl_work\@c@e@d1_tb\.svn\tmp\prop-base\
simulation\modelsim\rtl_work\@c@e@d1_tb\.svn\tmp\props\
simulation\modelsim\rtl_work\@c@e@d1_tb\.svn\tmp\text-base\
simulation\modelsim\rtl_work\clocks_and_reset\.svn\props\
simulation\modelsim\rtl_work\clocks_and_reset\.svn\tmp\prop-base\
simulation\modelsim\rtl_work\clocks_and_reset\.svn\tmp\props\
simulation\modelsim\rtl_work\clocks_and_reset\.svn\tmp\text-base\
simulation\modelsim\rtl_work\controller0\.svn\props\
simulation\modelsim\rtl_work\controller0\.svn\tmp\prop-base\
simulation\modelsim\rtl_work\controller0\.svn\tmp\props\
simulation\modelsim\rtl_work\controller0\.svn\tmp\text-base\
simulation\modelsim\rtl_work\controller1\.svn\props\
simulation\modelsim\rtl_work\controller1\.svn\tmp\prop-base\
simulation\modelsim\rtl_work\controller1\.svn\tmp\props\
simulation\modelsim\rtl_work\controller1\.svn\tmp\text-base\
simulation\modelsim\rtl_work\dual_port_ram\.svn\props\
simulation\modelsim\rtl_work\dual_port_ram\.svn\tmp\prop-base\
simulation\modelsim\rtl_work\dual_port_ram\.svn\tmp\props\
simulation\modelsim\rtl_work\dual_port_ram\.svn\tmp\text-base\
simulation\modelsim\rtl_work\gpio_controller\.svn\props\
simulation\modelsim\rtl_work\gpio_controller\.svn\tmp\prop-base\
simulation\modelsim\rtl_work\gpio_controller\.svn\tmp\props\
simulation\modelsim\rtl_work\gpio_controller\.svn\tmp\text-base\
simulation\modelsim\rtl_work\mem_block\.svn\props\
simulation\modelsim\rtl_work\mem_block\.svn\tmp\prop-base\
simulation\modelsim\rtl_work\mem_block\.svn\tmp\props\
simulation\modelsim\rtl_work\mem_block\.svn\tmp\text-base\
simulation\modelsim\rtl_work\mux_usb_c\.svn\props\
simulation\modelsim\rtl_work\mux_usb_c\.svn\tmp\prop-base\
simulation\modelsim\rtl_work\mux_usb_c\.svn\tmp\props\
simulation\modelsim\rtl_work\mux_usb_c\.svn\tmp\text-base\
simulation\modelsim\rtl_work\parallel\.svn\prop-base\
simulation\modelsim\rtl_work\parallel\.svn\props\
simulation\modelsim\rtl_work\parallel\.svn\text-base\
simulation\modelsim\rtl_work\parallel\.svn\tmp\prop-base\
simulation\modelsim\rtl_work\parallel\.svn\tmp\props\
simulation\modelsim\rtl_work\parallel\.svn\tmp\text-base\
simulation\modelsim\rtl_work\parallel_new\.svn\props\
simulation\modelsim\rtl_work\parallel_new\.svn\tmp\prop-base\
simulation\modelsim\rtl_work\parallel_new\.svn\tmp\props\
simulation\modelsim\rtl_work\parallel_new\.svn\tmp\text-base\
simulation\modelsim\rtl_work\parallel_rx\.svn\prop-base\
simulation\modelsim\rtl_work\parallel_rx\.svn\props\
simulation\modelsim\rtl_work\parallel_rx\.svn\text-base\
simulation\modelsim\rtl_work\parallel_rx\.svn\tmp\prop-base\
simulation\modelsim\rtl_work\parallel_rx\.svn\tmp\props\
simulation\modelsim\rtl_work\parallel_rx\.svn\tmp\text-base\
simulation\modelsim\rtl_work\power_controller\.svn\props\
simulation\modelsim\rtl_work\power_controller\.svn\tmp\prop-base\
simulation\modelsim\rtl_work\power_controller\.svn\tmp\props\
simulation\modelsim\rtl_work\power_controller\.svn\tmp\text-base\
simulation\modelsim\rtl_work\spi\.svn\prop-base\
simulation\modelsim\rtl_work\spi\.svn\props\
simulation\modelsim\rtl_work\spi\.svn\text-base\
simulation\modelsim\rtl_work\spi\.svn\tmp\prop-base\
simulation\modelsim\rtl_work\spi\.svn\tmp\props\
simulation\modelsim\rtl_work\spi\.svn\tmp\text-base\
simulation\modelsim\rtl_work\usb_double_buffer\.svn\props\
simulation\modelsim\rtl_work\usb_double_buffer\.svn\tmp\prop-base\
simulation\modelsim\rtl_work\usb_double_buffer\.svn\tmp\props\
simulation\modelsim\rtl_work\usb_double_buffer\.svn\tmp\text-base\
simulation\modelsim\rtl_work\usb_interface\.svn\props\
simulation\modelsim\rtl_work\usb_interface\.svn\tmp\prop-base\
simulation\modelsim\rtl_work\usb_interface\.svn\tmp\props\
simulation\modelsim\rtl_work\usb_interface\.svn\tmp\text-base\
simulation\modelsim\rtl_work\usb_rx\.svn\props\
simulation\modelsim\rtl_work\usb_rx\.svn\tmp\prop-base\
simulation\modelsim\rtl_work\usb_rx\.svn\tmp\props\
simulation\modelsim\rtl_work\usb_rx\.svn\tmp\text-base\
simulation\modelsim\rtl_work\usb_tx\.svn\props\
simulation\modelsim\rtl_work\usb_tx\.svn\tmp\prop-base\
simulation\modelsim\rtl_work\usb_tx\.svn\tmp\props\
simulation\modelsim\rtl_work\usb_tx\.svn\tmp\text-base\
source
CED1.v
CED1.v.bak
clocks_and_reset.v
clocks_and_reset.v.bak
controller0.v
controller0.v.bak
controller1.v
gpio_controller.v
gpio_controller.v.bak
mem_block.v
mux_usb_c.v
power_controller.v
power_controller.v.bak
spi.v
spi.v.bak
sport0.v
sport0.v.bak
synchronizer.v
usb_double_buffer.v
usb_interface.v
usb_interface.v.bak
usb_rx.v
usb_tx.v
.svn
MegaFunctions
dual_port_ram.bsf
source\.svn\prop-base\
source\.svn\props\
source\.svn\tmp\prop-base\
source\.svn\tmp\props\
source\.svn\tmp\text-base\
source\MegaFunctions\.svn\props\
source\MegaFunctions\.svn\tmp\prop-base\
source\MegaFunctions\.svn\tmp\props\
source\MegaFunctions\.svn\tmp\text-base\
test_and_sim
AD7760.do
ADT_6_reads.do
CED1_tb.vt
CED1_tb.vt.bak
csim.do
default_waves.do
first_sport0.do
first_sport0.gate.do
lin.do
power_en.do
sim.do
SRAM_WR_RD.do
three_packet_usb_loopback.do
.svn
test_and_sim\.svn\prop-base\
test_and_sim\.svn\props\
test_and_sim\.svn\tmp\prop-base\
test_and_sim\.svn\tmp\props\
test_and_sim\.svn\tmp\text-base\
