编写varilog程序,使fpga与上位机进行通信，上位机能够给fpga发送指令，fpga也能够将数据发送到上位机。

利用rs232，使fpga与上位机进行通信，利用quartus的pll锁相环模块产生50MHZ时钟，然后对50MHZ时钟进行分频，产生频率为115200的信号作为通信的波特率，fpga发送和接收数据都是一位一位的进行。

chuankou
incremental_db
db
chuankou1.asm.rpt
chuankou1.bdf
chuankou1.cdf
chuankou1.done
chuankou1.fit.rpt
chuankou1.fit.smsg
chuankou1.fit.summary
chuankou1.flow.rpt
chuankou1.jdi
chuankou1.map.rpt
chuankou1.map.smsg
chuankou1.map.summary
chuankou1.pin
chuankou1.pof
chuankou1.qpf
chuankou1.qsf
chuankou1.sof
chuankou1.sta.rpt
chuankou1.sta.summary
control.bsf
countN.bsf
countN.v
countN.v.bak
dashu1.bsf
dashu1.v
dashu1.v.bak
fasong1.bsf
fasong1.v
fasong1.v.bak
fenpin.bsf
fenpin.v
fenpin10000.bsf
fenpin10000.v
fenpin10000.v.bak
fenpin96.bsf
fenpin96.v
hengding.bsf
hengding.v
hengding.v.bak
PLL.bsf
PLL.v
PLL_25MxN.v
Reset_Gen.bsf
Reset_Gen.v
Reset_Gen.v.bak
serial_receive8.bsf
serial_receive8.v
serial_receive8.v.bak
serial_tran.bsf
stp1.stp
Trans_serial_two_channel1.bsf
Trans_serial_two_channel1.v
Trans_serial_two_channel8.bsf
Trans_serial_two_channel8.v
Trans_serial_two_channel8.v.bak