SDLX处理器（5级流水线，32位）

This project is about implementation of SDLX a 32-bit RISC processor on Xilinx Sparatan-3 FPGA. I, alongwith, Rajiv Kumar implemented the same. Following are the salient features - 1. 5-stage pipeline (IF, ID, EX, LSU, WB) 2. Hazard Handling (RAW are possible in this design) 3. Data Forwarding (from EX, LSU and WB to EX) 4. Cache modeling (instruction cache, data cache and corresponding arbiter)

ashishb_rajiv_SDLX_Final_Code_submission_snapshot8
ashish_rajiv_Lab 3 Submission code snapshot8.ipf_ISE_Backup
coregen
Block_RAM_8bit_blk_mem_gen_v2_4_xst_1.lso
testing_block.prj
Dist_RAM_8bit_wide.asy
testing_block_summary.xml
Lab2_ashishb_rajiv code snapshot 4.ipf
Distributed_ROM_for_IF.xco
bcd_driver.v
Lab2_ashishb_rajiv code snapshot 7.ipf
testing_block.ncd
testing_block_pad.txt
IF.xst
MemoryArbiter.prj
testing_block_guide.ncd
testing_block.bgn
ngdbuild.xmsgs
testing_block.lfp
PipelinedProcessor.prj
Dist_RAM_32bit_wide.veo
D_cache_L1.v
ashish_rajiv_Lab 3.ipf
Dcache.stx
testing_block_prev_built.ngd
Dist_RAM_32bit_wide_xmdf.tcl
testing_block.cmd_log
Distributed_ROM_for_IF.vhd
ashish_rajiv_Lab 2 Submission.ipf_ISE_Backup
Dist_RAM_32bit_wide.vhd
Block_RAM_8bit.vhd
Dist_RAM_8bit_wide_xmdf.tcl
D_FF.v
ashish_rajiv_Lab 3 Submission code snapshot6.ipf_ISE_Backup
_pace.lfp
Dist_RAM_8bit_wide_readme.txt
templates
Lab2_ashishb_rajiv code snapshot 3.ipf
Lab2_ashishb_rajiv code snapshot 8.ipf
reg_file.v
LSU.v
testing_block.ut
PipelinedProcessor_backup.v
instruction testing.doc
Distributed_ROM_for_IF.ngc
regfile
Lab2_ashishb_rajiv code snapshot 6.ipf
Lab2_ashishb_rajiv code snapshot 5.ipf
Dist_RAM_32bit_wide.xco
Lab1_ashishb_rajiv.ise
blk_mem_gen_ds512.pdf
test.mem
map.xmsgs
Dist_RAM_8bit_wide_flist.txt
Dist_RAM_8bit_wide.sym
MemoryArbiter.v
blk_mem_gen_release_notes.txt
testing_block.pcf
Distributed_ROM_for_IF.v
ashish_rajiv_Lab 3 Submission code snapshot6.ipf
IF.stx
Dcache.prj
ashish_rajiv_Lab 3 Submission code snapshot7.ipf
_pace.ucf
Lab1_ashishb_rajiv_backup.ipf
SDLX.doc
testing_block.lso
ashish_rajiv_Lab 3 Submission code snapshot1.ipf
Lab1_ashishb_rajiv_ise9migration.zip
testing_block.xpi
testing_block.par
trce.xmsgs
Block_RAM_8bit.xco
timing.twr
testing_block.v
testing_block_map.ngm
Dist_RAM_8bit_wide.v
if_blockram_init.coe
testing_block.syr
Block_RAM_8bit.vho
Dist_RAM_8bit_wide.vho
testing_block.ngd
Dist_RAM_8bit_wide.vhd
_impact.cmd
Distributed_memory
PipelinedProcessor.xst
if.v
Block_RAM_8bit_blk_mem_gen_v2_4_xst_1_vhdl.prj
counter.v
data_memory_gen
par.xmsgs
ashish_rajiv_Lab 3 Submission code snapshot7.ipf_ISE_Backup
_impact.log
PipelinedProcessor.stx
testing_block.drc
counter.ucf
testing_block_map.ncd
Block_RAM_8bit_xmdf.tcl
I_cache_L1.v
MemoryArbiter.stx
Distributed_ROM_for_IF.asy
testing_block.twr
Dist_RAM_32bit_wide.sym
ControlPath_summary.html
ForwardingUnit.v
counter_pad.txt
Dist_RAM_8bit_wide.mif
ashish_rajiv_Lab 3 Submission code snapshot8.ipf
instruction set.doc
ControlPath.v
if_blockram
Distributed_ROM_for_IF.veo
Block_RAM_8bit.asy
Dist_RAM_32bit_wide.asy
Lab1_ashishb_rajiv.ntrc_log
Icache.prj
testing_block_map.mrp
Dist_RAM_8bit_wide.xco
IF.prj
testing_block.ngr
Lab1_ashishb_rajiv.restore
testing_block.ngc
EX.v
Dist_RAM_32bit_wide.ngc
WB.v
Dist_RAM_32bit_wide.v
testing_block.stx
Block_RAM_8bit.ngc
testing_block.xst
testing_block.bld
Lab2_ashishb_rajiv code snapshot 6.ipf_ISE_Backup
Distributed_ROM_for_IF.sym
Distributed_ROM_for_IF.vho
testing_block_map.map
ID.v
Dcache.xst
SRAMinitwriter.v
Dist_RAM_8bit_wide.veo
Dist_RAM_32bit_wide.vho
ashish_rajiv_Lab 2 Submission.ipf
testing_block.unroutes
Lab1_ashishb_rajiv.ipf_ISE_Backup
reg_file_backup1.v
Block_RAM_8bit.v
Block_RAM_8bit_readme.txt
Block_RAM_8bit.sym
_pace.cel
_ngo
Dist_RAM_32bit_wide_readme.txt
testing_block.pad
ashish_rajiv_Lab 2 Submission
Block_RAM_8bit.veo
_xmsgs
Lab1_ashishb_rajiv.ise_ISE_Backup
bitgen.xmsgs
Distributed_ROM_for_IF_flist.txt
Distributed_ROM_for_IF_readme.txt
testing_block_map.mfp
ashish_rajiv_Lab 3 Submission code snapshot3.ipf_ISE_Backup
Icache.xst
ashish_rajiv_Lab 3 Submission code snapshot2.ipf
MemoryController.v
counter_summary.html
Distributed_ROM_for_IF_xmdf.tcl
testing_block_summary.html
MemoryArbiter.xst
DM.v
testing_block.twx
Block_RAM_8bit_flist.txt
constants.v
ashish_rajiv_Lab 3 Submission code snapshot4.ipf_ISE_Backup
testing_block_pad.csv
alu.v
xst
DM
Distributed_ROM_for_IF.mif
test.coe
testing_block.bit
regfile.v
testing_block_usage.xml
Dist_RAM_32bit_wide.mif
ashish_rajiv_Lab 3 Submission code snapshot4.ipf
__ISE_repository_Lab1_ashishb_rajiv.ise_.lock
Dist_RAM_32bit_wide_flist.txt
Dist_RAM_8bit_wide.ngc
PipelinedProcessor.v
ashish_rajiv_Lab 3 Submission code snapshot3.ipf
Icache.stx
Lab2_ashishb_rajiv code snapshot 2.ipf
xst.xmsgs