Xilinx IIC IP

由 Xilinx 提供的 IIC 接口，使用 AXI interface。 Features ‧ AXI interface is based on the AXI4-Lite interface ‧ Master or slave operation ‧ Multi-master operation ‧ Software selectable acknowledge bit ‧ Arbitration lost interrupt with automatic mode switching from master to slave ‧ Calling address identification interrupt with automatic mode switching from master to slave ‧ START and STOP signal generation and detection ‧ Repeated START signal generation ‧ Acknowledge bit generation and detection ‧ Bus busy detec ‧ Fast mode 400 KHz operation or standard mode 100 KHz ‧ 7-bit or 10-bit addressing ‧ General call enable or disable ‧ Transmit and receive FIFOs - 16 bytes deep ‧ Throttling ‧ General purpose output, 1 bit to 8 bits wide ‧ Dynamic Start and Stop generation ‧ Filtering on the SCL and SDA signals to eliminate spurious pulses

axi_iic_v2_0
bd
component.xml
doc
hdl
ttcl
utils
xgui