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FPGA 乒乓球

  • 资源大小:2.23 MB
  • 上传时间:2021-06-30
  • 下载次数:0次
  • 浏览次数:1次
  • 资源积分:1积分
  • 标      签: Verilog

资 源 简 介

此代码基于cyclone III开发。通过一排LED充当乒乓球,模拟打乒乓的游戏

文 件 列 表

__Previews
PLL.vPreview
ADD.bsf
ADD.v
db
.cmp.kpt
Final.(0).cnf.cdb
Final.(0).cnf.hdb
Final.(1).cnf.cdb
Final.(1).cnf.hdb
Final.(10).cnf.cdb
Final.(10).cnf.hdb
Final.(11).cnf.cdb
Final.(11).cnf.hdb
Final.(12).cnf.cdb
Final.(12).cnf.hdb
Final.(13).cnf.cdb
Final.(13).cnf.hdb
Final.(2).cnf.cdb
Final.(2).cnf.hdb
Final.(3).cnf.cdb
Final.(3).cnf.hdb
Final.(4).cnf.cdb
Final.(4).cnf.hdb
Final.(5).cnf.cdb
Final.(5).cnf.hdb
Final.(6).cnf.cdb
Final.(6).cnf.hdb
Final.(7).cnf.cdb
Final.(7).cnf.hdb
Final.(8).cnf.cdb
Final.(8).cnf.hdb
Final.(9).cnf.cdb
Final.(9).cnf.hdb
Final.asm.qmsg
Final.asm.rdb
Final.asm_labs.ddb
Final.cbx.xml
Final.cmp.bpm
Final.cmp.cdb
Final.cmp.hdb
Final.cmp.idb
Final.cmp.logdb
Final.cmp.rdb
Final.cmp_merge.kpt
Final.cuda_io_sim_cache.45um_ff_1200mv_0c_fast.hsd
Final.cuda_io_sim_cache.45um_ss_1200mv_85c_slow.hsd
Final.db_info
Final.eda.qmsg
Final.fit.qmsg
Final.hier_info
Final.hif
Final.ipinfo
Final.lpc.html
Final.lpc.rdb
Final.lpc.txt
Final.map.ammdb
Final.map.bpm
Final.map.cdb
Final.map.hdb
Final.map.kpt
Final.map.logdb
Final.map.qmsg
Final.map.rdb
Final.map_bb.cdb
Final.map_bb.hdb
Final.map_bb.logdb
Final.pre_map.hdb
Final.pti_db_list.ddb
Final.root_partition.map.reg_db.cdb
Final.routing.rdb
Final.rtlv.hdb
Final.rtlv_sg.cdb
Final.rtlv_sg_swap.cdb
Final.sgdiff.cdb
Final.sgdiff.hdb
Final.sld_design_entry.sci
Final.sld_design_entry_dsc.sci
Final.smart_action.txt
Final.sta.qmsg
Final.sta.rdb
Final.sta_cmp.8_slow_1200mv_85c.tdb
Final.tis_db_list.ddb
Final.tiscmp.fast_1200mv_0c.ddb
Final.tiscmp.fastest_slow_1200mv_0c.ddb
Final.tiscmp.fastest_slow_1200mv_85c.ddb
Final.tiscmp.slow_1200mv_0c.ddb
Final.tiscmp.slow_1200mv_85c.ddb
Final.tmw_info
Final.vpr.ammdb
logic_util_heursitic.dat
PLL_altpll.v
prev_cmp_Final.asm.qmsg
prev_cmp_Final.eda.qmsg
prev_cmp_Final.fit.qmsg
prev_cmp_Final.map.qmsg
prev_cmp_Final.qmsg
prev_cmp_Final.sta.qmsg
debug.log
DEC.bsf
DEC.v
DFF3.bdf
DFF3.bsf
DFF8.bdf
DFF8.bsf
Final.bdf
Final.qpf
Final.qsf
Final.qws
Final.vwf
Final_assignment_defaults.qdf
Final_nativelink_simulation.rpt
FP4.bdf
FP4.bsf
incremental_db
compiled_partitions
README
LHTCL.bdf
LHTCL.bsf
MSDCD.bsf
MSDCD.v
output_files
Final.asm.rpt
Final.done
Final.eda.rpt
Final.fit.rpt
Final.fit.smsg
Final.fit.summary
Final.flow.rpt
Final.jdi
Final.map.rpt
Final.map.summary
Final.pin
Final.sof
Final.sta.rpt
Final.sta.summary
greybox_tmp
output_files
PLL.qip
PLL.bsf
PLL.ppf
PLL.qip
PLL.v
PLL_bb.v
PLLJ_PLLSPE_INFO.txt
SEL.bsf
SEL.v
simulation
modelsim
qsim
XD.bdf
XD.bsf

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