fpga-sra-core

This is the first release of a FPGA project for short read alignment. The top module is a usr_logic file, which includes 5 major interfaces: 1 HyperTransport interface, 2 DDR2 memory interfaces, and 2 LLDRAM interfaces. The interface IP cores are not included in this project, but the interface behavior within the usr_logic module follows the IP standard. The major components include a Seed Engine and two banded Needleman-Wunsch aligner.

sra_src_code
addr_fifo.v
Align4bp.v
Align8bp_v2.v
AlignConc.v
AlignModule_v2.v
AlignProcessor.v
AlignTop.v
DataReform.v
delaynw.v
dffn.v
duplicate_removal.v
DupPos_fifo.v
DupRemove2.v
DupRmv_engine2.v
fifo_generator_v5_2.v
hash.v
HyperTransport.v
info_buf.v
key_fifo.v
LineGen.v
MotherBoard_a.v
MotherBoard_b.v
out_fifo.v
peripheral_interface.v
PosExtract.v
PrimDataAnalysis.v
rbuf.v
ReadsOnChip.v
read_id_fifo.v
ref_offset_fifo.v
ref_pos_in_fifo.v
rpu0_interface.v
rpu1_interface_v2.v
ScoreSum2.v
score_rearrange.v
score_sel.v
score_update.v
SeedGen.v
SeedHash.v
SegUpdate2.v
SegUpdate3.v
sum_lv1.v
sum_lv2.v
sum_lv3.v
user_design.v
user_logic.v