mcsim

McSimA+ is a timing simulation infrastructure that models x86-based asymmetric manycore microarchitectures in detail for both core and uncore subsystems, including a full spectrum of asymmetric cores from single-threaded to multithreaded and from in-order to out-of-order, sophisticated cache hierarchies, coherence hardware, on-chip interconnects, memory controllers, and main memory.

Apps
md
script
list
mcsim_wrapper.c
McSim
Makefile
PTS.h
PTSMemoryController.cc
stream
PTSRBoL.h
PTSRBoL.cc
PTSTLB.cc
PTSO3Core.cc
PTSMemoryController.h
PTSDirectory.h
McSim.h
main.cc
McSim.cc
PTSXbar.cc
PTSCache.cc
PTSCore.h
PTSDirectory.cc
mcsim.mk
PTSXbar.h
PTSTLB.h
PTS.cc
PTSCore.cc
PTSCache.h
PTSO3Core.h
PTSComponent.h
PTSComponent.cc
Pthread
Makefile
PTS.h
EEPthreadSim.cc
PthreadOnce.h
PthreadCleanup.h
PthreadBarrier.h
PthreadCondAttr.h
PthreadScheduler.h
PthreadMutexAttr.h
PthreadJoin.h
EEPthreadScheduler.cc
PthreadSim.cc
PthreadKey.cc
PthreadKey.h
PthreadJoin.cc
PthreadCancel.cc
PthreadCleanup.cc
PthreadCond.cc
PthreadAttr.h
PthreadMutex.h
PthreadMalloc.h
PthreadScheduler.cc
PthreadAttr.cc
mypthreadtool.h
PthreadBarrier.cc
PthreadOnce.cc
PthreadCancel.h
PthreadUtil.cc
mypthreadtool.cc
mypthread.cc
PthreadCond.h
EEPthreadScheduler.h
mypthreadtool.mk
PTS.cc
PthreadMalloc.cc
PthreadSim.h
PthreadCondAttr.cc
PthreadMutex.cc
PthreadUtil.h
PthreadMutexAttr.cc
README
TraceGen
Makefile
tracegen.mk
tracegen.cc