vlsi-gate-simulation-in-dsch
资 源 简 介
1) Compares the performance of 6 T SRAM cell in DSCH in 45 and 65 nm technology.
2) Simulation of NOR gate in DSCH with various capacitance and various nm technology.
3)Layout in microwind of 6Tsram cell circuit which was built in DSCH.
文 件 列 表
vasu
vasu145.bmp
vasu165nm.bmp
vasu1~lay.bmp
vasu2~45.bmp
vasu2~lay.bmp
VASU_100FF.bmp
vasu_1_sram.JPG
VASU_1~DSCH.bmp
vasu_3_4_con.JPG
VASU_3~1.bmp
vasu_3~1ff.bmp
vasu~100ff~2.bmp
VASU~3~1.bmp
VASU~3~4~LAY.bmp
