DE2 练习源码2-2

FPGA DE2开发板  实验2第一部分VHDL硬件语言练习源码 Part II You are to design a circuit that converts a four-bit binary number V = v3v2v1v0 into its two-digit decimal equivalent D = d1d0. Table 1 shows the required output values. A partial design of this circuit is given in Figure 1. It includes a comparator that checks when the value of V is greater than 9, and uses the output of this comparator in the control of the 7-segment displays. You are to complete the design of this circuit by creating a VHDL entity which includes the comparator, multiplexers, and circuit A (d

part2
incremental_db
db
lab2part2.asm.rpt
lab2part2.done
lab2part2.fit.rpt
lab2part2.fit.summary
lab2part2.flow.rpt
lab2part2.map.rpt
lab2part2.map.summary
lab2part2.pin
lab2part2.pof
lab2part2.qpf
lab2part2.qsf
lab2part2.qsf.bak
lab2part2.qws
lab2part2.sof
lab2part2.tan.rpt
lab2part2.tan.summary
lab2part2.vhd
lab2part2.vhd.bak