lvds-4x-asynchronous-oversampling

This application note describes a method of capturing asynchronous communication using LVDS with SelectIO™ interface primitives. The method consists of oversampling the data with a clock of similar frequency (±100 ppm). This oversampling technique involves taking multiple samples of the data at different clock phases to get a sample of the data at the most ideal point. The SelectIO interface in 7 series FPGAs and Zynq®-7000 All Programmable SoCs can perform 4x asynchronous oversampling at 1.25 Gb/s. Oversampling is performed by using ISERDESE2 primitives. Clocks are generated from a mixed-mode clock manager (MMCME2_ADV) through dedicated high-performance paths between the components.

xapp523-lvds-4x-asynchronous-oversampling.pdf